TSMC Supply Chain Spotlight

Foundry nodes, sites in four countries, CoWoS packaging, suppliers and China

TSMC earned 79% of its third-quarter 2026 wafer revenue at 7nm and finer, and outside Taiwan only its Arizona fab makes any of those nodes; every CoWoS package is still assembled in Taiwan.

TSMC wafer revenue by node, third quarter 2026: 2nm 8%, 3nm 33%, 5nm 28%, 7nm 10%, 16nm and older 21%. Which nodes each TSMC location makes: Taiwan makes every node and all CoWoS packaging. Arizona makes 4nm now, with 3nm planned for 2027 and 2nm later. Kumamoto, Japan makes 12 to 28nm, with 3nm planned for 2028. Dresden, Germany will make 12 to 28nm from 2027. Nanjing, China makes 16 and 28nm. TSMC WAFER REVENUE BY NODE, 3Q 2026 2nm 8% 3nm 33% 5nm 28% 7nm 10% 16nm+ 21% 79% at 7nm and finer SOURCE: TSMC THIRD-QUARTER 2026 RESULTS, OCTOBER 2026. WHICH NODES EACH TSMC LOCATION MAKES 2NM 3NM 4/5NM 6/7NM 12-28NM COWOS Taiwan Arizona, US Kumamoto, Japan Dresden, Germany Nanjing, China IN PRODUCTION PLANNED: ARIZONA 3NM 2027, JAPAN 3NM 2028 EVERY CoWoS PACKAGE IS ASSEMBLED IN TAIWAN; ARIZONA WAFERS SHIP BACK FOR PACKAGING. SITES: TSMC FILINGS AND THE SITE FAB DATASET, OCTOBER 2026.
Revenue, 3Q 2026
$46.7B
7nm and finer
79%
HPC share
68%
Capex, 2026
$60-64B
Arizona 3nm volume
3Q 2027
Hub
Spotlights

Node mix

Four Node Families Earn Four-Fifths of the Revenue

TSMC wafer revenue by node, third quarter 2026
NodeShare of wafer revenueMain fabsExample products
N2 (2nm)8%Fab 20, Hsinchu; Fab 22, KaohsiungFirst gate-all-around node; volume since late 2025; phone and AI chips ramping
N3 (3nm)33%Fab 18, TainanNVIDIA Rubin, Google TPU Ironwood, AWS Trainium3, Apple A19 Pro
N5 and N4 (5nm class)28%Fab 18, Tainan; Fab 21, ArizonaNVIDIA Blackwell Ultra B300 on 4NP
N7 and N6 (7nm class)10%Fab 15, TaichungOlder GPUs, networking, I/O dies
16nm and older21%Fab 12, Fab 14, JASM, NanjingMicrocontrollers, image sensors, power management, RF

TSMC's third-quarter 2026 revenue was $46.7 billion, up 41.2% in dollars, with a 66.4% gross margin. High-performance computing, which covers AI accelerators, server CPUs and custom chips, was 68% of revenue and smartphones 21%. A16, which adds backside power delivery (Super Power Rail) to the 2nm transistor, follows in the second half of 2026. Node definitions are on Process Nodes.

Sites

Outside Taiwan, Only Arizona Makes Leading-Edge Wafers

  • Made in US
  • Some US volume
  • US planned
  • Made abroad
TSMC sites by node and US status
SiteNodeStatusUS status
Fab 20, Hsinchu and Fab 22, KaohsiungN2, A16Volume rampMade abroad
Fab 18, TainanN5, N3Volume; the largest leading-edge siteMade abroad
Fab 21 phase 1, PhoenixN4Volume since late 2024; first US Blackwell wafer October 2025Made in US
Fab 21 phase 2, PhoenixN3Tools moving in; volume scheduled for the third quarter of 2027US planned
Fab 21 phase 3, PhoenixN2, A16Construction; later this decadeUS planned
Arizona advanced packagingCoWoS, SoICPlanned; no production dateUS planned
JASM, Kumamoto12 to 28nm; 3nm in fab 2Fab 1 operating; fab 2 volume planned for 2028Made abroad
ESMC, Dresden12 to 28nmConstruction; production from 2027Made abroad
TSMC Nanjing16nm, 28nmOperating under a 2026 US annual licenseMade abroad
Placeholder: remaining TSMC rows from the fab dataset (Fab 12, Fab 14, Fab 15, AP6, AP7, Sony-TSMC Koshi)

TSMC has committed $165 billion to Arizona: six fabs, two advanced packaging plants and a research center. When it is complete, TSMC expects about 30% of its 2nm and more advanced capacity to be in Arizona. Today that site makes only 4nm, one of the four leading-edge node families above, and the first 3nm fab there is about a year from volume. Japan's second fab moved from 6nm to 3nm, with volume planned for 2028, and Germany's ESMC is a mature-node fab for car and industrial chips.

CoWoS packaging

Every CoWoS Package Is Still Assembled in Taiwan

CoWoS, TSMC's chip-on-wafer-on-substrate packaging, joins an AI processor to its HBM memory stacks on a silicon interposer. Capacity averaged about 96,000 wafers a month in 2026 and is expected to reach about 130,000 by the end of 2026 and about 260,000 by the end of 2028 (TrendForce, September 2026). NVIDIA takes close to 60% of it. All of that capacity is in Taiwan, at AP6 in Zhunan, AP7 in Chiayi and the Taichung CoWoS lines.

That makes Arizona wafers a round trip. Blackwell wafers made at Fab 21 since October 2025 ship back to Taiwan for CoWoS assembly. The first US option is Amkor's Peoria, Arizona plant, which is set to package TSMC Arizona wafers from early 2028; TSMC's own Arizona packaging plants have no production date. Detail is on CoWoS.

In the chip rings

TSMC Is in All 10 Chips the Site Tracks

  • Made in US
  • Some US volume
  • US planned
  • Made abroad
TSMC's role in the 10 tracked chips
ChipWhat TSMC suppliesUS status
NVIDIA Blackwell Ultra B300Logic die (4NP, Tainan and Arizona), interposer, CoWoS-L packagingSome US volume
NVIDIA RubinLogic die (N3P), HBM4 base die for SK hynix, CoWoS-L packagingMade abroad
AMD Instinct MI455XCompute dies (N2), base and I/O dies (N3P), SoIC and CoWoS-LMade abroad
Google TPU IronwoodLogic die (N3P), CoWoS packagingMade abroad
AWS Trainium3Logic die (N3P), CoWoS-R packagingMade abroad
Microsoft Maia 200Logic die (3nm), CoWoS packagingMade abroad
Tesla AI5Second-source logic die, Arizona and TaiwanUS planned
Huawei Ascend 910CSome 7nm dies made before the 2024 cutoff, per teardownMade abroad
SK hynix HBM4Base die (12nm class)Made abroad
Apple A19 ProLogic die (N3P), InFO packagingMade abroad
Placeholder: per-chip rows from sx_chip_rings (supplier like 'TSMC%')

Every one of the 10 chips in the site's supplier rings has a TSMC part in it, including the memory: SK hynix's HBM4 stack sits on a TSMC base die. The only US volume in those 80 supplier rows is the B300 logic die at Fab 21. The full matrix is on Chip Supplier Rings.

Its suppliers

TSMC Cannot Route Around ASML or Japanese Resist

What TSMC depends on. Tools: ASML EUV scanners from the Netherlands, the one input no other company can supply; Applied Materials and Lam Research tools, some built in the US; Tokyo Electron tracks and etch tools from Japan. Materials: 300mm wafers from Shin-Etsu and SUMCO; EUV and ArF photoresist from JSR, TOK and Shin-Etsu in Japan, about 95% of EUV resist; gases from Air Liquide and Linde plants in Taiwan. Memory for its CoWoS packages: HBM from SK hynix, Samsung and Micron. TOOLS ASML EUV SCANNERS, NETHERLANDS Applied, Lam DEPOSITION, ETCH, SOME US Tokyo Electron TRACKS, ETCH, JAPAN MATERIALS Shin-Etsu, SUMCO 300MM WAFERS, JAPAN JSR, TOK, Shin-Etsu EUV AND ARF RESIST, JAPAN Air Liquide, Linde GASES, MADE IN TAIWAN MEMORY SK hynix HBM3E AND HBM4, KOREA Samsung HBM4, KOREA Micron HBM3E, TAIWAN, JAPAN TSMC TAIWAN, ARIZONA, JAPAN, GERMANY, CHINA THE DEPENDENCY IT CANNOT ROUTE AROUND: ASML EUV SCANNERS AND JAPANESE EUV RESIST FILL SHOWS US STATUS: DARKER = MORE US VOLUME; GRAY = MADE ABROAD.

TSMC's own dependencies are narrower than its customers' dependence on it, but they are absolute in two places. Every EUV layer runs on an ASML scanner, and TSMC is ASML's largest EUV customer. Japanese suppliers make about 95% of EUV resist and most 300mm wafers. Toolmakers and their US build sites are on Wafer Fab Equipment and ASML EUV Scanner; resist and wafers are on Photoresist and Wafer Production.

China

China Exposure Is One Mature Fab and a Closed Customer List

  • Nanjing: TSMC's only China fab makes 16nm and 28nm wafers. Its validated end-user status, which let US tools ship without individual licenses, lapsed on December 31, 2025; the US granted an annual license for 2026 that covers operation and maintenance.
  • Customers: TSMC stopped shipping to Huawei in September 2020. A TSMC-made die found in an Ascend AI processor in 2024 traced to orders placed through Sophgo, and TSMC halted those shipments. Chinese AI chips now run mainly at SMIC; see Huawei and HiSilicon.
  • Controls: TSMC screens advanced-node orders from China against US rules on transistor count and HBM, covered on Process Design Kits.

Cost of spreading out

Overseas Fabs Cost TSMC Two Points of Margin

Spreading out costs margin. TSMC's chief financial officer put the gross-margin drag from overseas fabs at close to two points in 2026, widening to three to four points over the next several years as more Arizona fabs open. Capital spending for 2026 is budgeted at $60 billion to $64 billion, of which $40.6 billion was spent in the first nine months, and the company says 2026 to 2028 spending will significantly exceed the previous three years. Fourth-quarter 2026 revenue is guided at $52.3 billion to $54.3 billion.

Record

Page Record

Covers
TSMC node mix and revenue, sites by node and US status, Arizona, Japan and Germany expansion, CoWoS capacity and location, role in the site's chip supplier rings, tool and material dependencies, China exposure and overseas cost
Sources
TSMC third-quarter 2026 results and management report (October 2026); TSMC earnings call coverage, XenoSpectrum (October 2026); TSMC Arizona $165 billion announcement (March 2025); Nikkei via EMSNow on Arizona fab 2 (December 2025); TrendForce CoWoS capacity (September 2026); The Standard on the Nanjing annual license (January 1, 2026); SemiconductorX fab dataset and chip supplier rings (October 2026)
Last verified
October 2026