How oxide grows
Thermal Oxide Is Made From the Wafer Itself
Oxidation turns the top of the silicon wafer into silicon dioxide, the best insulator and the best interface silicon can have.
Oxidation heats the wafer to between 800 and 1,200 °C in oxygen or steam, and the silicon surface turns into silicon dioxide (SiO2). Unlike deposition, nothing is added from outside except oxygen: the film is made of the wafer's own silicon. Each nanometer of oxide consumes about 0.44 nm of silicon, so 100 nm of oxide sits 44 nm below the original surface and 56 nm above it.
Growing into the crystal is what gives thermal oxide its value. The silicon-to-oxide interface forms below the old surface, away from whatever contamination sat on it, and has fewer electrical defects than any deposited film can match. That interface quality made silicon, not germanium, the material of the integrated circuit in the 1960s.
Growth slows as the film thickens, because oxygen has to diffuse through the oxide already formed to reach the silicon. Thin films grow at a rate set by the surface reaction, and thick films at a rate set by diffusion; the Deal-Grove model from 1965 still describes both regimes.
Where it is used
A Handful of Oxidations, Mostly in the Transistor
| Use | Purpose | Typical thickness |
|---|---|---|
| Pad oxide | Stress buffer under the silicon nitride hard mask that defines shallow trench isolation (STI) | 5 to 15 nm |
| STI liner | Grown on the trench walls before the CVD fill; rounds corners and repairs etch damage | 5 to 20 nm |
| Sacrificial oxide | Screens implants and removes damaged silicon; stripped afterward | 10 to 30 nm |
| Interfacial layer | Bottom of the high-k metal gate (HKMG) stack in advanced logic | About 1 nm |
| Gate oxide, mature nodes | The gate dielectric itself in planar CMOS at 65nm and coarser, analog, MCUs and MEMS | 1.5 to 10 nm |
| Power device gate and field oxide | Silicon IGBTs and MOSFETs; silicon carbide (SiC) MOSFETs | 50 to 200 nm |
| Field oxide (LOCOS) | Thick isolation in older processes; replaced by STI below 0.25 µm | 200 to 600 nm |
Oxidation is a conditional step, not part of every pass through the front-end loop. A logic wafer is oxidized a handful of times, nearly all of them in transistor formation; the interconnect stack above it uses deposited dielectrics instead. Where each step sits in the flow is on Front-End Fabrication.
Dry and wet
Dry Oxide for Quality, Steam for Thickness
| Dry (O2) | Wet (steam) | |
|---|---|---|
| Growth rate | Slow | Several times faster at the same temperature |
| Thickness range | About 1 to 20 nm | 20 nm to more than 1 µm |
| Film quality | Densest film; best interface | Lower density; some hydrogen in the film |
| Steam source | None | Pyrogenic: hydrogen burned in oxygen at the tube inlet |
| Main uses | Gate, interfacial and pad oxide | Field, sacrificial and power device oxide |
Two newer modes fill the gap. Rapid thermal oxidation (RTO) in a single-wafer lamp chamber controls films below 2 nm with a heating cycle of seconds, and in-situ steam generation (ISSG) reacts hydrogen and oxygen directly at the wafer surface for thin, high-quality oxide at low pressure. Plasma and radical oxidation run at lower temperatures where the thermal budget is already spent.
After high-k
Thermal Oxide Now Sits Under the Gate, Not in It
Thermal SiO2 was the gate dielectric from the 1960s until about the 45nm node. As it thinned toward 1.2 nm, electrons tunneled straight through it and gate leakage became unmanageable. Intel's 45nm process in 2007 replaced most of it with hafnium oxide deposited by atomic layer deposition, which has a higher dielectric constant and can be physically thicker for the same electrical effect.
A thin oxide survives under the high-k film because hafnium oxide sitting directly on silicon makes a poor interface. That interfacial layer, about 1 nm thick, is grown by RTP, ISSG or chemical oxidation and still controls much of the transistor's mobility and reliability. Gate-all-around transistors at TSMC N2, Intel 18A and Samsung SF2 must grow it on all four sides of each nanosheet.
SiC and power
SiC Power Chips Still Depend on a Grown Gate Oxide
Silicon carbide power MOSFETs, used in EV inverters and fast chargers, depend on a thermal gate oxide, and SiC oxidizes poorly. The reaction is slower than on silicon, it must also release carbon, and the leftover carbon creates interface traps that cut channel mobility. Producers anneal the oxide in nitric oxide (NO) to passivate those traps, and the gate oxide is one reason SiC MOSFETs have lower channel mobility than silicon devices.
Silicon IGBTs and power MOSFETs use thick gate and field oxides grown in batch furnaces, which keeps furnace demand strong at 200mm and mature 300mm fabs. Device context is on SiC and GaN Power Modules and SiC Power Fabs.
Equipment
Japanese Furnaces and US Rapid Thermal Tools
Oxidation runs on two kinds of tool. Vertical batch furnaces load 100 to 150 wafers into a quartz tube and run for hours; they dominate thick oxides, mature fabs and memory. Single-wafer rapid thermal processing (RTP) chambers heat one wafer with lamps for seconds and handle the thinnest, most controlled films at the leading edge. The same platforms run diffusion and dopant anneals.
- Made in US
- US planned
- Made abroad
| Vendor | Headquarters | Platforms | Where tools are built | US status |
|---|---|---|---|---|
| Kokusai Electric | Tokyo, Japan | Vertical batch furnaces for oxidation, diffusion and LPCVD; leading share in batch tools | Japan (Toyama) | Made abroad |
| Tokyo Electron (TEL) | Tokyo, Japan | TELINDY vertical batch furnaces | Japan | Made abroad |
| ASM International | Almere, Netherlands | A400-series vertical furnaces | Netherlands and Singapore | Made abroad |
| Applied Materials | Santa Clara, CA | Vantage and Radiance RTP; ISSG oxidation | US and Singapore | Some US volume |
| Mattson Technology | Fremont, CA (owned by Beijing E-Town Dragon) | RTP, millisecond anneal, dry strip | US and Germany | Some US volume |
| NAURA | Beijing, China | Vertical furnaces for oxidation and diffusion | China | Made abroad |
Furnaces are the step where Chinese tools have gone furthest. TrendForce reports that NAURA furnaces make up more than 60% of the oxidation and diffusion tools on SMIC's 28nm lines. Tool families are on Thermal Processing Equipment.
Gases and quartz
Oxygen, Hydrogen and Fused Quartz
Oxidation consumes high-purity oxygen and hydrogen, with nitrogen for purge, delivered from the four-company industrial gas supply of Air Liquide, Linde, Air Products and Taiyo Nippon Sanso; see Process Gases. Chlorine sources such as trans-dichloroethylene are added to some dry oxidations to getter sodium and other metals.
The tubes, liners and boats that hold wafers at 1,000 °C or more are fused quartz from Heraeus, Shin-Etsu Quartz, Tosoh and Momentive Technologies, with silicon carbide parts for the hottest steps. Much of the high-purity quartz sand behind fused-quartz ware and crystal-growing crucibles is mined at Spruce Pine, North Carolina, where Hurricane Helene shut the mines for weeks in 2024. See Quartzite to Polysilicon.
Record
Page Record
- Covers
- Thermal oxidation growth, uses and thicknesses, dry and wet modes, the shift to high-k gates, SiC gate oxide, equipment vendors and inputs
- Sources
- B. E. Deal and A. S. Grove, Journal of Applied Physics (1965); Intel 45nm high-k metal gate disclosure (2007); TrendForce (NAURA furnace share at SMIC 28nm, January 2026); company product pages for Kokusai, TEL, ASM, Applied Materials and Mattson (October 2026)
- Last verified
- October 2026