Semiconductor Photomask Deliverables
Photomasks — also known as reticles — are precision quartz plates with patterned chromium or phase-shifted layers that define the circuitry of each chip layer. They are essential consumables in the photolithography process, providing the blueprint that is repeatedly projected onto wafers. Photomasks are fabricated in specialized mask shops and delivered to fabs in sealed containers for use inside lithography scanners.
Role in the Supply Chain
- Produced externally by dedicated mask shops or captive facilities.
- Shipped to fabs as deliverables, not manufactured in-house during wafer processing.
- Each process technology requires dozens to hundreds of unique masks.
- Critical for scaling to advanced nodes (EUV masks at 7 nm, 5 nm, 3 nm and beyond).
Types of Photomasks
- Binary Masks: Opaque chromium patterns on quartz; standard for mature nodes.
- Phase-Shift Masks (PSM): Enhance resolution by altering light phase through transparent regions.
- Attenuated PSM: Semi-transparent regions provide better image contrast.
- EUV Masks: Multilayer reflective masks (Mo/Si stacks) for extreme ultraviolet lithography.
- Multi-Patterning Mask Sets: Double or quadruple patterning requires multiple masks per layer.
Mask Comparison Table
| Mask Type | Wavelength | Complexity | Primary Use | Representative Suppliers |
|---|---|---|---|---|
| Binary Mask | 193 nm (DUV) and older | Low | Mature nodes, legacy ICs | DNP, Toppan, Photronics |
| Phase-Shift Mask (PSM) | 193 nm (ArF Immersion) | Medium | Sub-65 nm nodes, resolution enhancement | Toppan, SK-Electronics |
| Attenuated PSM | 193 nm | Medium–High | Double patterning, tighter CDs | DNP, Photronics |
| EUV Mask | 13.5 nm (EUV) | Very High | 7 nm and below, advanced logic/memory | DNP, Toppan, captive TSMC/Samsung/Intel |
Mask Set Complexity by Node
| Process Node | Approx. Mask Count | Patterning Approach | Notes |
|---|---|---|---|
| 65 nm | ~20–25 masks | Single exposure, mostly binary masks | Legacy but still in automotive/IoT |
| 28 nm | ~30–35 masks | Double patterning begins | Widely used for cost-sensitive SoCs |
| 14/10 nm | ~45–55 masks | Quadruple patterning (193i) | Complex, cost-driving node generation |
| 7 nm | ~60–70 masks | Mix of EUV and multi-patterning | First widespread EUV adoption |
| 5 nm | ~70–80 masks | Heavier EUV usage | Flagship Apple, TSMC, Samsung designs |
| 3 nm | ~85–100 masks | Mostly EUV with advanced pellicles | Highest current mask set complexity |
Mask Manufacturing Process
- Mask Writing: Electron-beam writers pattern chromium/absorber layer.
- Etching: Removes unwanted absorber to create the design.
- Inspection: Defect detection using AIMS, SEM, and actinic inspection (for EUV).
- Repair: Focused ion beam (FIB) or e-beam repair of mask defects.
- Pellicle Application: Thin protective membrane mounted to prevent particle contamination during use.
Representative Vendors
- Dai Nippon Printing (DNP, Japan): Major global supplier of advanced photomasks.
- Toppan Photomasks (Japan): Leading merchant mask shop with global fabs.
- Photronics (U.S.): Large independent mask maker serving logic, memory, and display fabs.
- SK-Electronics (Japan): Specialized in advanced photomasks, including EUV.
- Intel, Samsung, TSMC (Captive): Internal mask-making capacity for advanced nodes.
Handling & Delivery
- Masks are shipped in sealed containers with anti-static and vibration protection.
- In fab, masks are stored in automated stockers and delivered to scanners in reticle pods (RSPs).
- Pellicles are used to keep particles off mask surfaces during exposure.
- Cleanroom automation ensures masks never contact open air once inside the fab.
Mask Usage in Fabs
- Each mask is loaded into a lithography scanner/stepper for patterning wafers.
- A single photomask may be used thousands of times before replacement.
- Mask defectivity directly translates into yield loss across entire wafer lots.
- EUV masks are particularly sensitive, requiring defect-free multilayers and pellicles.
Market Outlook
The photomask market is projected to exceed $6–7 billion by 2030, driven by the complexity of advanced-node designs and EUV adoption. Each shrink increases the number of masks required per chip design, boosting demand at leading-edge foundries. EUV masks and pellicle technologies remain strategic choke points in the global semiconductor supply chain.
Mask Set Economics
Mask sets are a major NRE (non-recurring engineering) cost driver. Costs scale with layer count, resolution enhancement, inspection/repair complexity, and EUV adoption. The table below shows typical industry ranges; actuals vary by design size, OPC/RET complexity, and vendor.
| Process Node | Approx. Mask Count | Typical Mask Set Cost (USD) | Primary Cost Drivers |
|---|---|---|---|
| 65 nm | ~20–25 | $0.2M – $0.5M | Binary/PSM mix, modest OPC, DUV inspection |
| 40/45 nm | ~25–30 | $0.4M – $0.8M | More layers, tighter CDs, enhanced RET |
| 28 nm | ~30–35 | $0.8M – $1.5M | Double patterning (193i), higher OPC effort |
| 16/14 nm | ~40–50 | $1.5M – $3M | Multiple multi-patterned layers, complex inspection/repair |
| 10/7 nm | ~60–70 | $3M – $6M | First EUV layers + residual multi-patterning, pellicles |
| 5 nm | ~70–80 | $6M – $12M | More EUV layers, tighter defectivity/specs, actinic inspection |
| 3 nm | ~85–100 | $10M – $20M+ | Heavy EUV usage, advanced pellicles, extreme OPC/RET |
Design teams often prototype on a mature node to de-risk logic and firmware, then port to an advanced node once functionality stabilizes—reducing mask respins and overall NRE.