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Semiconductor Supply Chain Overview



The semiconductor supply chain runs from mined quartzite and refined chemicals to finished electronic products. Materials and design come first. Wafers are made in fabs, then tested, assembled, packaged and integrated into modules and products, and the finished chips serve the end markets that set demand. Each stage has its own suppliers, equipment and chokepoints, and a failure at any one of them stops output at every stage after it.

Concentration is high at nearly every stage. Shin-Etsu Chemical and Sumco, both Japanese, supply about half of the world's 300mm silicon wafers. AGC and Hoya are the only volume makers of extreme ultraviolet (EUV) mask blanks. Synopsys, Cadence and Siemens EDA hold about 75% of the chip design software market. TSMC makes about 90% of sub-5nm wafers, ASML is the only supplier of EUV scanners, and TSMC CoWoS capacity gates AI accelerator output from NVIDIA and AMD.


Semiconductor Supply Chain Stages

StageWhat happensMain chokepointsCoverage
Materials and process inputsMining and refining of quartzite, gallium, germanium and rare earths; production of ultra-high-purity gases, chemicals, photoresist and CMP slurriesGeographic concentration, export controls, qualification cycles of up to a decadeProcess Inputs Overview
Wafer productionCrystal growing, slicing, polishing and epitaxy turn polysilicon into substratesFive producers hold about 85% to 90% of 300mm capacitySilicon Wafer Production
MasksMask blanks, pellicles and photomasks carry each circuit layer into lithographyTwo EUV mask blank makers; 70 to 100+ masks per advanced designEUV Mask Blanks and Pellicles; Photomasks and Reticles
Design, EDA and IPFabless companies design chips with licensed IP and electronic design automation (EDA) softwareThree EDA vendors; ARM for processor IP; tape-out costs near $500 million at 3nmFabless Design and IP Cores; EDA Tools
Front-end fabrication500 to 1,000 process steps build transistors and interconnect on the wafer over three to four monthsTSMC at the leading edge; lines cost $15 billion to $20 billion at 2nmFront-End Wafer Fabrication; Manufacturing Process Flow
Fab equipmentLithography, deposition, etch, implant, cleaning, metrology, CMP and thermal toolsASML, Applied Materials, Lam Research, Tokyo Electron and KLA supply nearly all advanced-node toolsWafer Fab Equipment; Fab Equipment Categories
Wafer sort testEach die is tested on the wafer before assemblyTwo companies dominate automated test equipmentWafer Sort Test
Back-end assembly and packagingDicing, die attach, wire bond or flip-chip connection, encapsulation and final testASE, Amkor and JCET hold more than 60% of outsourced assembly and test (OSAT)Back-End Assembly and Packaging
Advanced packagingMultiple dies joined through fan-out, 2.5D interposers or 3D stackingTSMC CoWoS capacity; Ajinomoto Build-up Film (ABF) substratesAdvanced Packaging Overview
Module integrationPackaged dies combined with power delivery, thermal management and boards into compute, memory and automotive modulesInterconnect standards (NVLink, UCIe, CXL); power delivery above 1,000W per AI moduleModule Integration
EMS and OEMsBoard assembly, system test and final productsFoxconn, Pegatron and Quanta for consumer devices; Wiwynn, Quanta and Inventec for AI serversEMS and OEMs

Materials and IP

The upstream stage supplies everything a fab consumes and everything a design needs before the first wafer starts. It covers raw and refined materials, process gases and chemicals, silicon and compound wafers, mask blanks and photomasks, and the design layer of fabless companies, EDA tools and IP cores. Contamination or a supply cut in any input reduces wafer yield and fab output directly.


Fab and Assembly

Manufacturing runs in four segments: front-end fabrication, wafer sort test, back-end assembly and packaging, and module integration. A polished wafer enters front-end fabrication, and a tested, system-ready module leaves module integration. Front-end fabrication accounts for 70% to 80% of a finished chip's manufacturing cost, and most of its 500 to 1,000 process steps repeat one loop of clean, deposit, pattern, etch, clean and measure.


Fab Operations

A leading-edge fab runs continuously on power, ultrapure water, cleanroom air handling, gas and chemical delivery, vacuum, vibration isolation and emissions abatement. These utilities decide where fabs can be built and how fast they come online. Power draw is a regional grid planning issue, water availability shaped site selection at TSMC Arizona, and seismic risk rules out some regions for leading-edge construction.


Chip Types and Sectors

Finished chips fall into device families: compute and logic, memory and storage, power, analog and mixed signal, RF and networking, optoelectronics, sensors and photovoltaic cells. Each family has its own process nodes, manufacturers and inputs. Demand comes from sectors such as AI datacenters, electric vehicles, smartphones, robotics and satellites, and several sectors often pull on the same supply at once. The same TSMC N5 wafers serve NVIDIA AI GPUs, Apple smartphone SoCs and automotive ADAS chips, and the same SiC power modules serve EV inverters, battery storage and solar inverters.


Risk, Policy and Workforce


Related Coverage

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