SemiconductorX > Semiconductor Supply Chain Overview
Semiconductor Supply Chain Overview
The semiconductor supply chain runs from mined quartzite and refined chemicals to finished electronic products. Materials and design come first. Wafers are made in fabs, then tested, assembled, packaged and integrated into modules and products, and the finished chips serve the end markets that set demand. Each stage has its own suppliers, equipment and chokepoints, and a failure at any one of them stops output at every stage after it.
Concentration is high at nearly every stage. Shin-Etsu Chemical and Sumco, both Japanese, supply about half of the world's 300mm silicon wafers. AGC and Hoya are the only volume makers of extreme ultraviolet (EUV) mask blanks. Synopsys, Cadence and Siemens EDA hold about 75% of the chip design software market. TSMC makes about 90% of sub-5nm wafers, ASML is the only supplier of EUV scanners, and TSMC CoWoS capacity gates AI accelerator output from NVIDIA and AMD.
Semiconductor Supply Chain Stages
| Stage | What happens | Main chokepoints | Coverage |
|---|---|---|---|
| Materials and process inputs | Mining and refining of quartzite, gallium, germanium and rare earths; production of ultra-high-purity gases, chemicals, photoresist and CMP slurries | Geographic concentration, export controls, qualification cycles of up to a decade | Process Inputs Overview |
| Wafer production | Crystal growing, slicing, polishing and epitaxy turn polysilicon into substrates | Five producers hold about 85% to 90% of 300mm capacity | Silicon Wafer Production |
| Masks | Mask blanks, pellicles and photomasks carry each circuit layer into lithography | Two EUV mask blank makers; 70 to 100+ masks per advanced design | EUV Mask Blanks and Pellicles; Photomasks and Reticles |
| Design, EDA and IP | Fabless companies design chips with licensed IP and electronic design automation (EDA) software | Three EDA vendors; ARM for processor IP; tape-out costs near $500 million at 3nm | Fabless Design and IP Cores; EDA Tools |
| Front-end fabrication | 500 to 1,000 process steps build transistors and interconnect on the wafer over three to four months | TSMC at the leading edge; lines cost $15 billion to $20 billion at 2nm | Front-End Wafer Fabrication; Manufacturing Process Flow |
| Fab equipment | Lithography, deposition, etch, implant, cleaning, metrology, CMP and thermal tools | ASML, Applied Materials, Lam Research, Tokyo Electron and KLA supply nearly all advanced-node tools | Wafer Fab Equipment; Fab Equipment Categories |
| Wafer sort test | Each die is tested on the wafer before assembly | Two companies dominate automated test equipment | Wafer Sort Test |
| Back-end assembly and packaging | Dicing, die attach, wire bond or flip-chip connection, encapsulation and final test | ASE, Amkor and JCET hold more than 60% of outsourced assembly and test (OSAT) | Back-End Assembly and Packaging |
| Advanced packaging | Multiple dies joined through fan-out, 2.5D interposers or 3D stacking | TSMC CoWoS capacity; Ajinomoto Build-up Film (ABF) substrates | Advanced Packaging Overview |
| Module integration | Packaged dies combined with power delivery, thermal management and boards into compute, memory and automotive modules | Interconnect standards (NVLink, UCIe, CXL); power delivery above 1,000W per AI module | Module Integration |
| EMS and OEMs | Board assembly, system test and final products | Foxconn, Pegatron and Quanta for consumer devices; Wiwynn, Quanta and Inventec for AI servers | EMS and OEMs |
Materials and IP
The upstream stage supplies everything a fab consumes and everything a design needs before the first wafer starts. It covers raw and refined materials, process gases and chemicals, silicon and compound wafers, mask blanks and photomasks, and the design layer of fabless companies, EDA tools and IP cores. Contamination or a supply cut in any input reduces wafer yield and fab output directly.
- Semiconductor Process Inputs Overview
- Silicon Wafer Production Overview
- Sputtering Targets
- EUV Mask Blanks and Pellicles
- Photomasks and Reticles
- Fabless Design and IP Cores
- EDA Tools
Fab and Assembly
Manufacturing runs in four segments: front-end fabrication, wafer sort test, back-end assembly and packaging, and module integration. A polished wafer enters front-end fabrication, and a tested, system-ready module leaves module integration. Front-end fabrication accounts for 70% to 80% of a finished chip's manufacturing cost, and most of its 500 to 1,000 process steps repeat one loop of clean, deposit, pattern, etch, clean and measure.
- Fab and Assembly Hub
- Fab Facilities
- Semiconductor Manufacturing Process Flow
- Semiconductor Business Models: fab, foundry, IDM, fabless, OSAT, EMS and OEM
Fab Operations
A leading-edge fab runs continuously on power, ultrapure water, cleanroom air handling, gas and chemical delivery, vacuum, vibration isolation and emissions abatement. These utilities decide where fabs can be built and how fast they come online. Power draw is a regional grid planning issue, water availability shaped site selection at TSMC Arizona, and seismic risk rules out some regions for leading-edge construction.
Chip Types and Sectors
Finished chips fall into device families: compute and logic, memory and storage, power, analog and mixed signal, RF and networking, optoelectronics, sensors and photovoltaic cells. Each family has its own process nodes, manufacturers and inputs. Demand comes from sectors such as AI datacenters, electric vehicles, smartphones, robotics and satellites, and several sectors often pull on the same supply at once. The same TSMC N5 wafers serve NVIDIA AI GPUs, Apple smartphone SoCs and automotive ADAS chips, and the same SiC power modules serve EV inverters, battery storage and solar inverters.
Risk, Policy and Workforce
- Bottlenecks: the Semiconductor Bottleneck Atlas ranks the chokepoints with the most cross-sector impact.
- Reshoring: U.S. Semiconductor Reshoring covers CHIPS Act awards and the fab buildout by state.
- Sovereignty constraints: U.S. Semiconductor Sovereignty Constraints covers the grid, permitting, water, workforce, export and capital limits on domestic manufacturing.
- Governance and compliance: the GRC Hub covers export controls, supply chain integrity and environmental and safety standards.
- Workforce: Semiconductor Workforce and Talent covers the engineer and technician pipeline for new fabs.
- Companies: Company Spotlights profile TSMC, NVIDIA, Intel, ASML, Samsung and other key suppliers.
Related Coverage
Fab & Assembly Hub | Fab Operations Hub | Chip Types Hub | Sectors Hub | GRC Hub | Workforce Hub | Company Spotlights | Semiconductor Bottleneck Atlas