AI & Machine Learning
Semiconductors

AI and machine learning is the fastest-growing semiconductor demand sector on the map and the one most responsible for reshaping the global supply chain in the 2023-2030 period. The demand signal is not gradual - it is a step function. The emergence of large language models at commercial scale in 2023, followed by multimodal foundation models, agentic AI systems, and sovereign AI infrastructure programs, created a GPU and accelerator demand surge that TSMC, SK Hynix, and NVIDIA were structurally unable to satisfy on short timescales. That mismatch between demand step-change and supply lead times - 18-24 months for new wafer capacity, 12-18 months for HBM stacking capacity, 12+ months for CoWoS advanced packaging - is the defining supply chain dynamic of this sector through 2030.

The SX supply chain lens on AI and ML has three structural arguments. First, the AI semiconductor supply chain is not a GPU supply chain - it is a stacked bottleneck system in which wafer starts, HBM production, CoWoS packaging capacity, and networking silicon must all scale in lockstep, and any one layer becoming the constraint halts the whole system. Second, NVIDIA's ~80% market concentration in AI training accelerators makes the AI semiconductor supply chain more fragile to single-supplier disruption than any other sector at comparable scale. Third, the custom ASIC wave at hyperscalers (Google TPU, Amazon Trainium, Microsoft Maia, Meta MTIA) is real and structurally motivated - but it competes for the same TSMC N3/N5 capacity and CoWoS packaging queue as NVIDIA, meaning it does not relieve the upstream supply constraint even as it displaces NVIDIA at the device level for some workloads.

Related Coverage: AI Accelerators | HBM | CoWoS Packaging | GPUs | ASICs | Bottleneck Atlas | Edge Inference SoCs

The Stacked Bottleneck System

An AI training cluster is not a GPU - it is a system in which the GPU die is one component in a four-layer supply chain stack, each layer with independent capacity constraints and lead times. Understanding why AI chip supply cannot respond quickly to demand requires understanding all four layers simultaneously.

Layer one is the logic die: the GPU or accelerator chip itself, manufactured at TSMC N3 or N5 using EUV lithography. TSMC has roughly 90% market share at sub-5nm. ASML supplies essentially 100% of EUV scanners. Adding a new EUV scanner takes 12-18 months from order to installation. Adding a new fab building takes 3-5 years. TSMC N3 and N5 capacity is physically constrained by the number of installed EUV scanners and the floor space to run them. Layer two is HBM (High Bandwidth Memory): each NVIDIA H100 or B200 GPU requires 6-8 HBM3 or HBM3e stacks, each stack comprising 8-12 DRAM dies bonded with through-silicon vias (TSVs) and assembled with a base die. SK Hynix, Samsung, and Micron are the only three suppliers capable of HBM production, and SK Hynix alone supplies the majority of HBM for NVIDIA's current generation. HBM capacity expansion requires building new DRAM fab capacity specifically configured for TSV bonding - a 2-3 year lead time process. Layer three is CoWoS advanced packaging: NVIDIA H100 and B-series GPUs use TSMC's CoWoS-L or CoWoS-S interposer packaging to integrate the logic die with HBM stacks on a silicon interposer. CoWoS capacity is separate from wafer start capacity - TSMC has limited CoWoS lines, and CoWoS was not a high-volume process before the AI GPU demand surge. Adding CoWoS capacity requires building new packaging lines, a 12-18 month lead time independent of wafer capacity. Layer four is networking: an AI training cluster requires high-speed interconnect between GPUs within a node (NVLink) and between nodes (InfiniBand or high-radix Ethernet). Networking silicon - Broadcom's Tomahawk/Jericho series, Nvidia's Quantum InfiniBand ASICs, Marvell's Teralynx - is a separate supply chain with its own capacity constraints and lead times.

The practical consequence: even if TSMC adds N5 wafer capacity, GPU production is constrained by HBM availability. Even if HBM production expands, GPU shipment is constrained by CoWoS packaging slots. Even if all three expand in parallel, cluster deployment is constrained by networking silicon and the power infrastructure to run the cluster. The stacked bottleneck system means that relief in one layer does not proportionally relieve the system constraint - the next layer becomes the binding constraint instead.

AI Semiconductor Device Map

NVIDIA Concentration — The Single-Supplier Risk

NVIDIA holds approximately 80% of the AI training accelerator market by revenue as of 2025. This concentration is the most significant single-supplier risk in the entire semiconductor supply chain - not because NVIDIA is a fragile company, but because the dependencies compound in both directions. On the demand side, the AI sector's infrastructure investment decisions, software development ecosystems, and operational cost structures are all built around CUDA - NVIDIA's proprietary parallel computing platform. CUDA lock-in is not primarily a contractual phenomenon; it is an ecosystem phenomenon. The millions of GPU-hours of developer time optimized for CUDA represent a switching cost that no hardware alternative can eliminate through superior performance alone. On the supply side, NVIDIA's concentration means that TSMC N3/N5 CoWoS-packaged HBM-integrated GPUs are effectively a single-SKU supply chain for the AI training market - any disruption to TSMC, to CoWoS capacity, to SK Hynix HBM supply, or to NVIDIA itself propagates immediately to global AI infrastructure buildout.

The China export control dimension compounds the concentration risk. BIS export controls have progressively restricted NVIDIA's ability to sell its highest-performance AI chips to Chinese customers. The A100 was restricted in October 2022; the H100 was restricted at the same time; China-specific variants (A800, H800, H20) have been successively restricted as BIS closed performance loopholes. The effect is a shrinking addressable market for NVIDIA's highest-margin products in the world's second-largest AI investment market, while Huawei Ascend captures the displaced demand domestically. This bifurcation does not reduce NVIDIA's supply chain dependencies - TSMC still manufactures NVIDIA's chips; SK Hynix still supplies HBM - but it concentrates NVIDIA's revenue in the US, European, and allied-nation markets and removes a demand buffer that would otherwise absorb excess supply in down cycles.

AI Training Accelerator Landscape

The Custom ASIC Wave — Hyperscaler Silicon Strategy

Every major hyperscaler has an active custom AI ASIC program. Google has operated TPUs since 2016. Amazon's Trainium (training) and Inferentia (inference) programs are at second-generation commercial production. Microsoft's Maia 100 inference ASIC entered Azure deployments in 2024. Meta's MTIA (Meta Training and Inference Accelerator) v2 is in production for internal recommendation model inference. The collective strategic motivation is identical across all five companies: reduce dependence on NVIDIA's pricing power and supply allocation decisions, capture the efficiency gains available from workload-specific silicon optimization, and develop silicon design capability as a strategic asset independent of vendor roadmaps.

The supply chain implication that is routinely underanalyzed: custom hyperscaler ASICs compete for the same TSMC N3/N5 wafer capacity and the same CoWoS advanced packaging capacity as NVIDIA GPUs. When Google tapes out a new TPU generation at TSMC N5, it occupies wafer starts that cannot simultaneously serve NVIDIA, AMD, or any other customer. The custom ASIC wave does not reduce the upstream supply constraint - it redistributes who benefits from the constrained supply. For TSMC and for HBM suppliers, the custom ASIC wave is an additional demand source on top of NVIDIA and AMD, not a substitution for them. This is why TSMC's N3/N5 capacity remains oversubscribed despite the emergence of multiple GPU alternatives.

Note on the custom ASIC landscape as of April 2026: NVIDIA's $20B acqui-hire of Groq (December 2025) and its subsequent integration as Groq 3 LPU within the Vera Rubin platform represents a structural shift in the custom silicon competitive dynamic. Rather than competing against inference-optimized ASICs, NVIDIA has absorbed the most commercially validated one into its own platform - the same strategy used with Mellanox networking (2020). The supply chain implication: Groq 3 LPU is manufactured by Samsung at 4nm (not TSMC), making it the first significant NVIDIA platform chip not manufactured at TSMC - a meaningful if partial supply chain diversification. The Vera Rubin platform now comprises seven chips across five rack-scale systems: Rubin GPU, Vera CPU, NVLink 6 switch, ConnectX-9 SuperNIC, BlueField-4 DPU, Groq 3 LPU, and Spectrum-X CPO (co-packaged optics Ethernet switch).

HBM — The Memory Bottleneck

High Bandwidth Memory is the second layer of the stacked bottleneck and arguably the most supply-constrained single component in the AI chip system. HBM is not conventional DRAM - it is a 3D-stacked memory assembly in which 8-12 thin DRAM dies are bonded vertically using through-silicon vias (TSVs), then connected to the GPU logic die via a silicon interposer in the CoWoS package. The TSV bonding process requires specialized equipment, dedicated fab space, and is yield-limited at a different rate than conventional DRAM. HBM die yield, TSV bonding yield, and CoWoS assembly yield all multiply together - meaning system-level HBM supply is lower than the raw DRAM production rate implies.

SK Hynix achieved a significant first-mover advantage in HBM3e - the generation required for NVIDIA H100 and B-series GPUs - and was effectively the sole volume supplier of NVIDIA-qualified HBM3e through most of 2024. Samsung's HBM3e program experienced qualification delays, reducing its effective supply contribution. Micron's HBM3e qualification at NVIDIA completed in 2024, providing the first meaningful US-based HBM supply for AI GPUs and partially relieving SK Hynix's near-monopoly position. The HBM4 generation - required for next-generation GPU architectures including NVIDIA Rubin and AMD MI400 - requires further process innovation (bottom die logic, wider I/O, GDDR7-derived cell technology) and will trigger another qualification cycle across all three suppliers starting in 2026.

China Bifurcation — The AI Compute Split

The AI compute market bifurcation between Western and Chinese ecosystems is covered in depth on the Sectors Hub page. The supply chain specifics at the AI sector level are as follows. Huawei's Ascend 910B and 910C are manufactured by SMIC using DUV multi-patterning at approximately N+1/N+2 process nodes - equivalent to roughly 7nm-class density without EUV access. The performance gap to NVIDIA B-series at TSMC N4P is real and is estimated at 2-3 architectural generations in raw compute density. Huawei partially closes this gap through software optimization (CANN framework, MindSpore), custom packaging approaches that differ from CoWoS, and workload-specific tuning for Chinese LLM training tasks.

Beijing's September 2025 directive instructing Chinese firms to cease purchasing NVIDIA GPUs and migrate to Huawei Ascend systems formalized what export controls had been progressively creating. The directive applies to AI training infrastructure for Chinese enterprises. The practical effect is that China's AI training infrastructure is becoming a separate ecosystem - not just a different GPU, but a different software stack (CUDA vs CANN), different interconnect (NVLink-equivalent Huawei implementation vs standard InfiniBand), different memory (domestic CXMT HBM development vs SK Hynix/Micron), and different deployment practices. The bifurcation is structural and likely permanent for this decade, with implications for which companies' AI infrastructure is vulnerable to which supply chain disruptions.

The gallium and germanium export controls imposed by China in 2023 represent the counter-leverage: both materials are used in compound semiconductor manufacturing (GaAs, GaN, InP) relevant to networking and RF components. China controls approximately 80% of global gallium production and 60% of global germanium production. The export controls have not yet materially disrupted Western AI semiconductor supply chains - gallium and germanium content in GPU dies is minimal - but they signal China's willingness to use upstream material control as a geopolitical instrument in the semiconductor competition.

Supply Chain Bottlenecks and Risk Factors (2026-2030)

Inference at the Edge — The Second AI Semiconductor Wave

Training cluster supply chain dynamics dominate the AI semiconductor narrative, but inference at scale - running trained models for end-user applications - is the demand driver that will ultimately determine the total semiconductor volume consumed by the AI sector. The training-to-inference ratio in compute hours is estimated at approximately 1:10 to 1:100 depending on model deployment scale: a model trained once is inferred millions or billions of times. As AI applications proliferate from hyperscaler products to enterprise software to consumer devices, inference compute demand will grow independently of training demand and at a different supply chain profile.

Inference workloads have different semiconductor requirements than training. Training maximizes throughput (FLOPS per second) and requires massive HBM bandwidth for gradient accumulation. Inference optimizes for latency (time to first token) and throughput-per-dollar at mixed precision (int8, fp8). The optimal inference silicon is not necessarily the same as the optimal training silicon - which is why custom inference ASICs (Google TPU v5e, Amazon Inferentia2, Meta MTIA) can achieve better performance-per-dollar for their specific workloads than a general-purpose training GPU. The NVIDIA Groq 3 LPU integration into the Vera Rubin platform (announced GTC 2026) is the most significant acknowledgment of this gap - NVIDIA absorbed Groq's SRAM-based low-latency inference architecture because GPU decode performance is insufficient for agentic AI token rates. Edge inference - running AI models on smartphones, laptops, vehicles, and robots - adds a further dimension: ultra-low power (milliwatts to watts, not kilowatts), form factor constraints, and on-device data privacy. Edge inference SoCs (Apple Neural Engine in A-series chips, Qualcomm Hexagon NPU in Snapdragon, NVIDIA Orin in automotive) are manufactured at mature-leading-edge nodes (N5-N4) and represent a growing share of AI-related wafer demand at TSMC.

The most extreme edge inference application announced as of GTC 2026 is the Space-1 Vera Rubin Module - the Rubin GPU architecture packaged for orbital datacenter and satellite deployment, delivering 25x H100 AI compute in a size-, weight-, and power-constrained module for use in satellites and space stations. Space-1 extends the inference edge from data centers to low Earth orbit, with NVIDIA partners including Aetherflux, Axiom Space, Kepler Communications, Planet Labs, Sophia Space, and Starcloud deploying NVIDIA compute (currently IGX Thor and Jetson Orin; Space-1 Module pending ship date) in active space missions. The primary unresolved engineering challenge is thermal management - orbital environments have no convection or conduction cooling, only radiation into space. See: Space & Defense Sector for full Space-1 supply chain analysis.

Key AI Semiconductor Suppliers

Cross-Sector Convergence

AI semiconductor demand intersects the broader supply chain in three primary ways. First, the TSMC N3/N5 allocation competition: AI GPU and custom ASIC programs compete for the same wafer starts as automotive ADAS SoCs (NVIDIA DRIVE Thor, Mobileye EyeQ6H), mobile SoCs (Apple A-series, Qualcomm Snapdragon), and PC processors (Apple M-series, AMD Ryzen). AI programs represent a growing share of TSMC's N5 revenue but automotive programs represent a growing strategic priority for TSMC given their qualification longevity and geopolitical significance. The competition is not resolved by market pricing alone - TSMC's allocation decisions reflect strategic customer relationships, long-term agreement commitments, and government policy pressure simultaneously.

Second, the datacenter power infrastructure convergence: AI cluster power density (10-120kW per rack for GB200 configurations) is driving demand for GaN-based server PSUs and advanced power delivery ICs at a scale that intersects with the same GaN supply chain serving EV onboard chargers and industrial power conversion. The GaN PSU supply chain was not sized for AI cluster power density at hyperscale buildout rates. This is the most underappreciated secondary constraint on AI cluster deployment - not the GPU or the HBM, but the power delivery silicon that feeds them.

Third, the edge inference expansion into automotive, robotics, and mobile: as AI model deployment moves from hyperscaler datacenters to edge devices - vehicles, robots, smartphones, industrial systems - the inference SoC supply chain intersects with automotive (NVIDIA DRIVE Thor, Mobileye EyeQ6), robotics (NVIDIA Orin for humanoid platforms), and mobile (Apple Neural Engine, Qualcomm Hexagon). These are not separate supply chains - they are competing allocations of the same TSMC N5 and N4 wafer capacity. AI edge inference growth does not reduce datacenter AI demand; it adds a parallel demand curve competing for the same foundry capacity.

Related Coverage: Bottleneck Atlas | AI Accelerators | HBM | CoWoS | U.S. Reshoring | Datacenter / HPC | Automotive & Mobility | Robotics & IoT

Cross-Network: ElectronsX Demand Side

AI semiconductor demand is visible on the EX side through the AV platforms directory, humanoid robot coverage, and datacenter infrastructure analysis where AI inference compute creates demand signals for power and cooling infrastructure.

EX: AV Platforms Directory | EX: Humanoid Robots | EX: Supply Chain Convergence Map

Key Questions — AI & ML Semiconductors

Why can't the AI chip shortage be solved by building more fabs? New fab capacity takes 3-5 years from groundbreaking to production volume. EUV scanners - the machines required to manufacture at N3/N5 - take 12-18 months to deliver after ordering, and ASML produces approximately 50-60 High-NA EUV systems per year globally. The capital cost of a new leading-edge fab is $15-20 billion. Even with unlimited capital and political will, the physics of semiconductor manufacturing sets a floor on how fast supply can respond to a step-change in demand. The AI demand surge that began in 2023 will not see full supply response until 2027-2028 at the earliest - and by then, AI model complexity and cluster size requirements will have grown further.

Does the custom ASIC wave reduce AI supply chain risk? No - it redistributes risk within the same constrained supply chain. Google, Amazon, Microsoft, and Meta all manufacture their custom AI ASICs at TSMC N5, the same node as NVIDIA GPUs. Custom ASICs compete for the same CoWoS packaging capacity and, in the case of ASIC programs with HBM integration, the same HBM supply. The custom ASIC wave reduces NVIDIA's revenue concentration risk and gives hyperscalers more control over their silicon roadmaps - but it does not add foundry capacity, packaging capacity, or HBM capacity. The upstream supply chain constraint is unchanged; only the customer mix changes.

What is the realistic trajectory of the China AI compute gap? Huawei Ascend 910B/910C at SMIC N+1 is approximately 2-3 process generations behind NVIDIA B-series at TSMC N4P in raw compute density. This gap will not close while China lacks EUV access - which is the current and projected situation through at least 2030 given export control trajectories. Huawei can close some of the gap through architectural efficiency, larger cluster configurations, and software optimization, but the physics of transistor density without EUV sets a ceiling on how far this can go. Chinese AI developers working exclusively on Huawei Ascend will be operating at a structural compute disadvantage relative to NVIDIA-equipped Western peers for the foreseeable future - which is precisely why the Beijing directive mandating the transition is strategically significant: it accepts the performance penalty in exchange for supply security.

What is the significance of GaN PSU supply for AI clusters? NVIDIA's GB200 NVL72 configuration - a rack-scale system of 72 Blackwell GPUs - draws approximately 120kW of electrical power per rack. Legacy server PSU technology (silicon MOSFET, 12V architecture) cannot efficiently convert and distribute this power density. The industry transition to 48V rack power architecture using GaN-based PSU ICs enables higher conversion efficiency at the power densities required. GaN PSU ICs from Navitas, Infineon, and TI are the enabling semiconductor for this power architecture. As AI cluster buildout accelerates, GaN PSU demand is growing faster than the GaN supply base anticipated - making power delivery silicon an emerging secondary bottleneck behind GPU and HBM supply.

Related Coverage

Sectors Hub | AI Accelerators | GPUs | HBM | CoWoS Packaging | ASICs | Edge Inference SoCs | Bottleneck Atlas | U.S. Reshoring | Tesla Terafab Supply Chain | Datacenter / HPC | Automotive & Mobility | Robotics & IoT