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Fab Facilities
A fab is not a factory. It is an industrial complex — continuously operating, drawing more electricity than most mid-sized cities, processing millions of gallons of ultrapure water per day, executing hundreds of process steps with nanometer-level tolerance control. And no two fabs are the same. A SiC power fab and a leading-edge logic fab share vocabulary — lithography, etch, deposition — but almost nothing else. Different substrates, different tools, different chemistries, different tolerances, different economics, different vendor supply chains.
Fab Facilities is organized into three categories: wafer fabs (the front-end transformation facilities), packaging and test operators (OSAT and captive), and the emerging standalone test facility layer.
Wafer Fabs — the wafer fabrication facility landscape. Fab archetypes, geographic distribution, operator profiles, CHIPS Act and EU Chips Act buildout status, individual fab profile pages.
Packaging & Test Operators — OSAT and captive packaging. ASE, Amkor, JCET, Powertech, Tongfu, Huatian at the merchant level; TSMC CoWoS, Samsung I-Cube, Intel Foveros at the foundry-captive level.
Test Facilities — standalone and co-located test facilities. Emerging as a distinct layer as HBM and advanced SoC test requirements exceed traditional OSAT capacity.
Fab Archetypes — Why a Fab Is Not a Fab
Semiconductor fabs partition into distinct archetypes that share vocabulary but operate as fundamentally different industrial systems. A SiC boule growth and device facility cannot produce a leading-edge logic chip regardless of capital invested — the substrate physics, tool configuration, and process chemistries are incompatible. The table below maps the major fab archetypes that define the global manufacturing landscape, each a separate supply chain and a separate strategic story.
| Archetype | Primary Outputs | Representative Operators | Structural Character |
|---|---|---|---|
| Leading-edge logic (≤5nm) | AI accelerators, flagship mobile SoCs, high-end server CPUs, automotive AV inference SoCs | TSMC (Fab 18 Hsinchu, Fab 21 Arizona); Samsung (Pyeongtaek, Taylor); Intel (Oregon, Arizona, Ohio — 18A ramp) | ~90% Taiwan-concentrated; $15–25B CapEx per line; 4–6 year greenfield timeline; three-operator market globally |
| Mature logic (14nm–180nm) | Automotive MCUs, industrial control ICs, mature SoCs, analog-adjacent mixed-signal | TSMC (many fabs); GlobalFoundries; UMC; SMIC; Vanguard; PSMC; Hua Hong | Broad foundry market; AEC-Q100 qualification creates 18–24 month switching costs; Chinese domestic capacity scaling aggressively |
| DRAM | Standard DRAM (DDR5, LPDDR5), HBM base dies for advanced packaging, mobile DRAM | Samsung (Pyeongtaek, Hwaseong); SK hynix (Icheon, M16); Micron (Taiwan, Japan, US CHIPS Act sites); CXMT (Hefei, scaling) | Three-operator Western market + scaling Chinese entrant; distinct process from logic (capacitor-over-bitline, buried wordline); HBM supply is where memory and packaging converge |
| 3D NAND | NAND flash for SSDs, mobile storage, data center storage | Samsung; SK hynix (including Solidigm); Kioxia / Western Digital joint venture; Micron; YMTC (China) | Highest-aspect-ratio etch in the industry (>200:1); vertical layer count (300+ layers) drives process complexity; distinct competitive dynamics from DRAM |
| SiC power | SiC MOSFETs, SiC Schottky diodes, SiC power modules for EV inverters, BESS, solar, VFDs | Wolfspeed (Mohawk Valley, post-Chapter 11); Infineon (Villach, Kulim); STMicro (Catania); onsemi (Bucheon, Hudson); Rohm; Bosch (Reutlingen); Mitsubishi Electric; SICC (China) | Physics-limited boule growth (1–2 weeks per crystal); nine-market demand convergence against one substrate funnel; 150mm to 200mm transition is the volume multiplier; Western restructuring versus Chinese scaling |
| GaN power and RF | GaN HEMTs for fast chargers, data center PSUs, RF front-ends, robot joint drives | Infineon / GaN Systems; Power Integrations; Navitas; EPC; Nexperia; Qorvo; Wolfspeed (RF); Sumitomo | GaN-on-Si (power) vs GaN-on-SiC (RF) substrate split; humanoid robot demand adds new demand curve for motor drive ICs; mature competitive market |
| Analog & mixed-signal | Precision analog ICs (BMS, current sense, temperature, gate drivers), BiCMOS mixed-signal, high-voltage BCD | Texas Instruments (Sherman TX 300mm analog); Analog Devices; STMicro; Microchip; Renesas; NXP; onsemi | TI-ADI duopoly in precision analog; 200mm fab ceiling historically — TI Sherman is the first major 300mm analog capacity expansion; humanoid and robot demand creates new pressure layer |
| CMOS image sensor (CIS) | Automotive cameras, mobile cameras, industrial machine vision, AR/VR sensors | Sony (~50–55% automotive market share); Samsung; onsemi; OmniVision; STMicro | Sony Japan concentration; BSI and stacked-die CIS is its own packaging discipline; automotive camera density multiplying per-vehicle count |
| MEMS | IMUs, pressure sensors, accelerometers, gyroscopes, MEMS microphones, ultrasonic transducers | Bosch; STMicro; TDK (InvenSense); Analog Devices; NXP; Infineon | Suspended-structure release is a unique process step; humanoid robot demand adds 3–8 IMU instances per unit; fragmented competitive market with high design differentiation |
| III-V compound semiconductor | InP for LiDAR emitters and photonics; GaAs RF front-ends; InGaAs APDs for LiDAR detection; VCSELs for LiDAR and face recognition | Qorvo; Lumentum; Coherent (II-VI); IQE (epi); Sumitomo; AXT (substrates); MACOM | InGaAs APD supply is a LiDAR scale-up chokepoint; VCSEL scaling for automotive and robot LiDAR; small substrate market with long qualification cycles |
| Silicon photonics | Coherent optics, silicon photonics transceivers, co-packaged optics for AI cluster interconnect | Intel; GlobalFoundries (Fotonix); TSMC (COUPE platform); TowerJazz; IMEC pilot line | Emerging but strategically critical for post-electrical AI interconnect; integration with CMOS logic is the differentiator; handful of operators scaling |
| Rad-hard & rad-tolerant | Radiation-hardened MCUs, FPGAs, SoCs, analog, and power for satellites, deep-space missions, strategic defense, nuclear systems; rad-tolerant COTS-screened parts for LEO commercial space | BAE Systems (Nashua NH); Honeywell (Plymouth MN); Microchip / Microsemi; AMD/Xilinx (space-grade); Texas Instruments (QMLV/QMLQ); SkyWater (Bloomington MN, DMEA Cat 1A trusted foundry); GlobalFoundries (trusted foundry at Malta NY); Teledyne e2v; SpaceX Terafab (AI7/D3 rad-tolerant inference, emerging) | US-concentrated due to DoD Trusted Foundry / DMEA accreditation requirements; mature-node dominant (90nm–250nm) because radiation hardening is better understood at these geometries; QML-V (space) and QML-Q (military) qualification regimes; no commercial foundry substitute for defense-grade parts |
The rad-hard and rad-tolerant archetype has structural properties that distinguish it from the other eleven. Production is almost entirely US-based and accreditation-gated — the DoD Defense Microelectronics Activity (DMEA) runs the Trusted Foundry program that qualifies suppliers to handle classified designs for defense and intelligence customers. Space-grade and defense-grade parts are qualified under QML-V (space) and QML-Q (military) tiers of MIL-PRF-38535. Europe has a parallel regime (ESCC) with a much smaller operator base. The customer pool is sovereign-coupled (DoD, NASA, NRO, DOE, commercial space primes) rather than commercial, and process nodes are typically mature (90–250nm) because radiation hardening is better characterized at larger geometries. The SpaceX Terafab AI7/D3 program is the most credible emerging path to radiation-tolerant inference compute at LEO constellation scale.
Packaging & Test Operators
Packaging and test facilities are distinct from wafer fabs — different operators, different equipment, different economics. The OSAT (Outsourced Semiconductor Assembly and Test) landscape handles the bulk of the back-end value chain, with captive packaging at leading-edge foundries (TSMC CoWoS, Intel Foveros, Samsung I-Cube) increasingly handling the most advanced work. The table below maps the packaging operator landscape.
| Operator Category | Representative Operators | Primary Capability |
|---|---|---|
| Merchant OSAT (Tier 1) | ASE Technology (Taiwan, global leader); Amkor Technology (US HQ, Korean and Taiwanese operations); JCET (China, third globally) | Full-range packaging from commodity wire bond to advanced flip-chip, system-in-package, and fan-out; broad customer base across foundry and IDM clients |
| Specialty OSAT | Powertech Technology (memory packaging specialty); SPIL (now part of ASE); Chipbond (memory and display driver); Tongfu Microelectronics (China); Huatian Technology (China) | Memory packaging, test-intensive services, specialty device packaging; regional concentration in Taiwan and China |
| Foundry captive packaging | TSMC (CoWoS at AP6, AP7, AP8 packaging facilities; SoIC); Samsung (I-Cube, X-Cube); Intel (Foveros, EMIB at Oregon and New Mexico); GlobalFoundries (FOPLP) | Leading-edge advanced packaging co-designed with foundry process; CoWoS is currently the binding constraint on AI accelerator shipment |
| IDM captive packaging | Intel (own back-end for Xeon, Core); Samsung (memory packaging); SK hynix (HBM packaging at Icheon); Micron (memory packaging) | Captive packaging integrated with IDM manufacturing strategy; HBM packaging at memory IDMs is a specific competitive advantage as HBM demand scales |
| Standalone test houses | ISE Labs (ASE-owned); King Yuan Electronics; ARDENTEC; Sigurd Microelectronics | Specialty test services, often for memory and high-complexity SoCs; HBM test capacity is emerging as a distinct bottleneck |
Notable Fab Facilities List
The fab database below covers logic foundries, memory fabs, SiC device fabs, compound semiconductor fabs, specialty analog fabs, rad-hard foundries, and advanced packaging facilities globally. Filter by fab type, country, process node, wafer size, operational status, or CHIPS Act/subsidy status. Last updated: April 2026.
Geographic Concentration — Key Supply Chain Facts
The following concentration facts establish the baseline supply chain risk profile of the global fab landscape. These are the most supply-chain-significant concentration points across all fab types.
Taiwan accounts for approximately 90% of global sub-5nm logic production (TSMC Hsinchu and Taichung) and a significant share of sub-7nm capacity. Samsung Pyeongtaek and Hwaseong in South Korea account for approximately 50-55% of global HBM production and a significant share of leading-edge DRAM and NAND. South Korea overall accounts for approximately 70% of global memory semiconductor production. China accounts for approximately 80% of global GaAs and GaN compound semiconductor substrate production (gallium supply) and approximately 80% of global refined gallium - the upstream material for GaAs, GaN, and InP devices. The United States accounts for approximately 10-12% of global semiconductor manufacturing value added, a share that the CHIPS Act is designed to increase toward 20% by 2030.
The most acute single-point concentrations are: TSMC Fab 18 (Hsinchu) for N3/N3E leading-edge logic; SK Hynix M16 (Icheon) for HBM3e and HBM4; WIN Semiconductors (Taiwan, Taoyuan) for GaAs foundry services; GlobalFoundries Fab 9 (Malta NY) for SiGe BiCMOS at mmWave-capable process nodes; Wolfspeed Durham NC for Western SiC substrate growth; BAE Systems Manassas VA for US rad-hard processor manufacturing; and Sony Semiconductor Kumamoto for flagship-tier CMOS image sensors. Each of these represents a supply chain dependency that affects multiple sectors and cannot be substituted on timescales shorter than 2-4 years even with unlimited capital.
Related Coverage
Fab Clusters | Nanofab List | Process Nodes & Lines | U.S. Reshoring | Wafer Fab Equipment | Bottleneck Atlas