Advanced Packaging Overview

Advanced semiconductor packaging combines multiple dies (logic, memory, I/O, accelerators and sensors) into one integrated module through high-density interconnect. It is the multi-die half of stage 3 in the semiconductor manufacturing flow; traditional back-end assembly wraps a single die in a protective package. The main advanced packaging families are fan-out wafer-level packaging (FOWLP), 2.5D packaging with dies side by side on a silicon interposer or silicon bridge, and 3D packaging with dies stacked vertically through through-silicon vias (TSVs) or copper-to-copper hybrid bonds.

As transistor scaling has slowed, packaging has become the main lever on system performance, and it is now the industry's most important supply chain choke point after extreme ultraviolet (EUV) lithography. Every NVIDIA H-series, B-series and Rubin GPU, every AMD MI300 and MI400 series accelerator and most hyperscaler custom AI silicon depend on TSMC CoWoS (Chip-on-Wafer-on-Substrate) capacity. Ajinomoto is the near-sole source of Ajinomoto Build-up Film (ABF), the laminate in advanced flip-chip ball grid array (FCBGA) substrates. Hybrid bonding tools for 3D integration below 10 µm pitch come mainly from BESI (with Applied Materials) and Tokyo Electron. These concentrations have put advanced packaging capacity into U.S. and allied industrial policy alongside leading-edge fab capacity.

Advanced Packaging Architectures

Advanced packaging architectures fall into three families: fan-out (redistribution layer (RDL) routing on a reconstituted wafer or panel), 2.5D (side-by-side dies on an interposer or bridge) and 3D (vertically stacked dies). Each foundry runs its own branded versions, outsourced semiconductor assembly and test (OSAT) providers run fan-out and system-in-package (SiP) lines, and each architecture has its own supply chain, customers and capacity.

2.5D Packaging: CoWoS, EMIB and I-Cube

2.5D integration places multiple dies side by side on a shared interconnect layer: a full silicon interposer (CoWoS, I-Cube), a small silicon bridge embedded in the organic substrate (EMIB) or an RDL interposer. It gives AI accelerators the bandwidth and latency needed to connect several high-bandwidth memory (HBM) stacks to a logic die, without the thermal and manufacturing difficulty of full 3D stacking.

• CoWoS (TSMC): the leading 2.5D architecture by revenue, bonding a logic die and two, four, eight or more HBM stacks onto an interposer that is then mounted on an organic substrate. CoWoS-S uses a silicon interposer, CoWoS-R an RDL interposer and CoWoS-L local silicon bridges. CoWoS capacity has limited AI accelerator production since 2023, even though TSMC has roughly doubled it each year. Variants, customers and capacity are covered on CoWoS Packaging.
• EMIB (Intel): a small silicon bridge embedded in an organic substrate that provides dense die-to-die wiring only where it is needed, avoiding the cost of a full interposer. EMIB is used in Intel Sapphire Rapids server CPUs with HBM and in multi-tile chiplet products, and its cost advantage is largest at moderate bandwidth. See EMIB.
• I-Cube (Samsung Foundry): a silicon interposer architecture similar to CoWoS, serving Samsung Foundry customers that need HBM integration, at smaller revenue scale and with fewer customers than CoWoS. See I-Cube.

3D Packaging: Foveros, SoIC and HBM Stacking

3D integration stacks dies vertically, connected through TSVs with solder micro-bumps or, in the newest generation, through direct copper-to-copper hybrid bonds. It gives the shortest interconnects (micrometers instead of millimeters), the lowest latency and the highest density, at the cost of harder thermal design and lower yield, since one bad die scraps the whole stack.

• Foveros (Intel): used in Meteor Lake and later client CPUs, with compute, graphics, I/O and system-on-chip (SoC) tiles stacked on a base die. Foveros uses TSVs and micro-bumps; Foveros Direct replaces the micro-bumps with hybrid bonding below 10 µm pitch. See Foveros.
• SoIC (TSMC): die-on-die stacking with hybrid bonding and no interposer, positioned as the 3D complement to CoWoS.
• HBM stacking: the volume driver for 3D integration. Each stack holds eight, 12 or 16 DRAM dies joined by TSVs on a base logic die, and HBM4, ramping through 2026, is the first generation to use hybrid bonding between dies. See HBM.

Architectures, thermal design and stack yield are covered on 3D IC Packaging.

Fan-Out Packaging: InFO, FO-WLP and FOPLP

Fan-out packaging embeds the die in a reconstituted wafer or panel and builds RDL wiring on top, spreading the die's I/O pads over a larger area than the die itself. That supports a higher pin count, removes the need for an organic substrate in many products and produces very thin packages suited to mobile devices.

• InFO (TSMC): TSMC's fan-out architecture, used in Apple A-series and M-series SoCs and in other mobile and wearable products. InFO-PoP (package-on-package) stacks memory on the logic die, InFO-oS places multiple dies on fan-out RDL and InFO_SoW (system-on-wafer) builds wafer-scale modules. InFO capacity has grown alongside CoWoS but serves a largely separate customer set. See InFO.
• FO-WLP: fan-out packaging at OSATs, led by ASE, Amkor and JCET, for mobile SoCs, RF front-end modules, automotive radar chips and consumer products. See FO-WLP.
• FOPLP: the same process on rectangular panels instead of round wafers, for higher throughput and lower cost per unit. Long promised as a cost breakthrough, it is now entering production at OSATs and foundry captive lines.

Packaging Substrates and Interposers

The substrate and interposer layer sits between the dies and the circuit board. Advanced packaging uses four substrate and interposer technologies, each with its own supplier concentration.

Advanced FCBGA substrate lead times stretched past 40 weeks during the AI buildout, and new capacity takes years and heavy capital to build. ABF goes into essentially every high-pin-count FCBGA substrate worldwide, so Ajinomoto's output directly limits advanced packaging output. Suppliers, glass and ceramic substrates are covered on Substrates and Interposers.

Hybrid Bonding

Hybrid bonding joins two planarized die surfaces with direct copper-to-copper and oxide-to-oxide bonds and no solder. It reaches pitches below 10 µm, against roughly 20 to 40 µm for micro-bumps, with much lower thermal and electrical resistance at the joint. HBM4, TSMC SoIC and Intel Foveros Direct all compete for a small installed base of hybrid bonders from BESI (with Applied Materials) and Tokyo Electron, which makes tool supply one of the tightest constraints on next-generation packaging. Technology and equipment detail is on Advanced Interconnects.

Captive and OSAT Advanced Packaging

Ten years ago most packaging was outsourced to OSATs. Leading-edge advanced packaging now runs in captive lines: TSMC runs CoWoS and InFO in Taiwan, Intel runs EMIB and Foveros in New Mexico, Oregon and Arizona, Samsung Foundry runs I-Cube and SAINT, and SK hynix packages its own HBM stacks. The interposer or bridge is made at the same foundry as the logic die and the packaging process is tuned together with the front-end process, so handing it to an outside OSAT would break that joint optimization.

ASE, Amkor and JCET serve the middle tier: FO-WLP and FOPLP for mobile and RF, substrate-based 2.5D for products that do not need silicon-interposer bandwidth, and high-volume fan-out for consumer SoCs. All three are investing heavily in advanced packaging, and Amkor's Arizona site, backed by the CHIPS Act, is the flagship Western packaging reshoring project. Operators, regions and packaging tiers are covered on OSAT Providers.

Advanced Packaging Bottlenecks

Advanced Packaging Industrial Policy

Governments now treat advanced packaging as a national security priority alongside leading-edge fab capacity. An AI accelerator cannot ship without CoWoS, CoWoS production is concentrated in Taiwan, and no Western alternative at equivalent scale is expected before the end of this decade. The U.S. CHIPS Act includes advanced packaging in its funding and incentives, and the European Chips Act also treats packaging as strategic. TSMC Arizona includes advanced packaging alongside front-end fabrication, and Amkor's Arizona facility is the flagship Western packaging project.

The Tesla Terafab vertical integration plan is a related response: where packaging, front-end and design must be optimized together, a company with the scale to do so brings all three in-house. The industry expects advanced packaging capacity to stay a constraint through the next decade even as new capacity opens, with concentration shifting from Taiwan toward a broader but still concentrated global footprint.

Related Coverage

CoWoS Packaging | InFO (Integrated Fan-Out) Packaging | Foveros Packaging | I-Cube Packaging | FO-WLP Packaging | 3D IC Packaging | SiP Packaging | 2.5D Packaging | Back-End Assembly Overview | Advanced Packaging Primer