Process Nodes & Technology Lines

Semiconductor process nodes and technology lines define how chips are manufactured and what capabilities a fabrication facility can deliver. While often used interchangeably, these terms describe different concepts: the process node refers to the transistor scaling and lithographic capability (e.g., 7nm, 5nm, 3nm), while a technology line refers to the actual manufacturing line inside a fab that produces chips at a given node or for a specific application domain. Understanding both is critical for mapping the semiconductor industry, assessing supply resilience, and forecasting market trends.

Process Nodes

• Definition: The nominal size of transistors or critical features in a chip, expressed in nanometers (nm).
• Performance Impact: Smaller nodes generally offer higher transistor density, faster switching speeds, and lower power consumption.
• Moore’s Law Context: Historically, nodes shrank every 18–24 months, though progress now relies on EUV lithography and advanced packaging.
• Foundry Differences: Node naming is not standardized — TSMC 5nm differs from Intel 5nm or Samsung 5nm in density and transistor design.
• Examples:
  • Leading edge: 2nm, 3nm (TSMC, Samsung, Intel)
  • Advanced: 5nm, 7nm (in mass deployment for AI/ML and HPC)
  • Mature: 14nm, 28nm, 40nm (common in automotive and industrial)
  • Legacy: 65nm, 90nm, 130nm+ (still critical for analog, rad-hard, and power devices)

Technology Lines

• Definition: The production line inside a fab dedicated to chips of a given node, specialty process, or customer requirement.
• Line Differentiation: A fab may run multiple lines at different nodes (e.g., one at 28nm, another at 65nm) depending on equipment and demand.
• Specialization:
  • Logic lines: High-performance CPUs, GPUs, SoCs
  • Memory lines: DRAM, NAND, HBM
  • Analog/power lines: Automotive-grade ICs, SiC/GaN power devices
  • Rad-hard lines: Legacy nodes optimized for reliability in space and defense
• Examples:
  • TSMC Fab 18 ? 3nm line (leading edge)
  • GlobalFoundries Malta (NY) ? 12nm/14nm specialty lines
  • Texas Instruments fabs ? 65nm analog/power lines
  • Intel D1X (Oregon) ? High-NA EUV pilot lines for sub-2nm

Market Segmentation by Node

Future Nodes & Technology Lines

The industry roadmap extends well beyond today’s 2nm–3nm technologies. Foundries and equipment suppliers are actively developing next-generation nodes and new process lines that push the limits of physics, materials, and economics. These efforts rely heavily on EUV lithography (and high-NA EUV), new transistor architectures, and 3D integration. At the same time, specialty lines for SiC, GaN, and compound semiconductors are being expanded in parallel to serve power electronics, automotive, and renewable energy sectors.

• 1.8nm / 2nm Lines:
  • TSMC, Samsung, and Intel are all racing to commercialize 2nm by mid-2020s.
  • Gate-All-Around (GAA) transistors replace FinFETs for improved power efficiency and density.
  • High-NA EUV lithography introduced for critical layers.
• 1nm & Sub-1nm Nodes:
  • Projected for the early 2030s, though definitions become less about geometry and more about performance scaling.
  • Research into 2D materials (e.g., MoS2) and carbon nanotube FETs (CNTFETs) as silicon successors.
  • Extreme materials challenges: line edge roughness, variability, and quantum effects.
• 3D Stacking & Chiplet Lines:
  • Increasingly important as Moore’s Law slows.
  • Advanced packaging (CoWoS, Foveros, 3D IC) enables multiple dies at different nodes to be combined in one package.
  • New “packaging fabs” may emerge as dedicated lines for 2.5D and 3D integration.
• Specialty Lines Beyond Silicon:
  • SiC and GaN process lines expanding globally, driven by EVs, renewables, and grid infrastructure.
  • Compound semiconductor fabs for RF (GaAs, InP) serving 5G/6G and satellite communications.
  • Dedicated rad-hard lines for aerospace and defense continue at mature geometries.

Strategic Outlook

• Rising Costs: Each new node adds tens of billions in R&D and fab investment.
• Geopolitical Competition: U.S., Taiwan, South Korea, Japan, and the EU are aligning subsidies to host next-gen fabs.
• Technology Diversification: Future performance gains may come more from heterogeneous integration than pure node scaling.
• Workforce Needs: Specialized talent in materials science, EUV optics, and design-technology co-optimization will be in high demand.

Strategic Importance

• Capacity Allocation: Leading-edge nodes (<5nm) are capacity-constrained, driving geopolitical and economic competition.
• Resilience: Mature and legacy nodes remain indispensable for automotive, industrial, and defense — shortages here can halt production lines.
• National Security: Governments view control of advanced node technology lines as a strategic imperative (CHIPS Act, EU Chips Act, Japan–Taiwan–US collaborations).
• Technology Futures: Beyond nodes, innovations in 3D stacking, chiplets, and advanced packaging increasingly determine performance gains.