Node names
Node Names Are Brands, Not Measurements
The nanometer number in a node name stopped matching any physical feature around 2009. TSMC N3, Samsung SF3 and Intel 3 share a number and little else. A node name today stands for a package of density, power and performance gains over the foundry's previous node, and each foundry counts differently.
| Measure | TSMC N2 | Intel 18A | Note |
|---|---|---|---|
| Transistor type | Gate-all-around nanosheet | Gate-all-around (RibbonFET) | Both left FinFET at this node |
| Backside power | No (comes with A16) | Yes (PowerVia) | Intel shipped backside power first |
| High-density SRAM bit cell | About 0.0175 µm² | 0.021 µm² | Smaller is denser; SRAM is a large share of AI chip area |
| Gain over prior node | About 15% more density than N3E for mixed designs; 25 to 30% less power | About 1.3 times the density of Intel 3 | Each foundry measures against its own prior node |
| Tightest metal pitch (M0) | Not disclosed | 32nm | Wiring pitch limits density as much as the transistor does |
The fair way to compare foundries is transistor density in millions per square millimeter, SRAM cell size, transistor type, whether power runs on the back, and yield maturity. The name alone says only where a node sits in its own foundry's sequence.
Transistor types
Every Recent Node Changed the Transistor Shape
Shrinking dimensions alone stopped improving transistors more than a decade ago, so each recent node has leaned on a new transistor shape. Each shape gives the gate a firmer grip on the channel, which cuts leakage when the transistor is off.
- FinFET raised the channel into a fin with the gate on three sides. Intel shipped it first, in 2012; TSMC and Samsung followed at 16nm and 14nm. TSMC N3 is still FinFET.
- Gate-all-around (GAA) stacks horizontal silicon sheets and wraps the gate around all four sides. Samsung shipped it first, at SF3 in 2022. TSMC N2 and Intel 18A both moved to GAA in late 2025.
- Backside power moves the power wiring from above the transistors to the back of the wafer, leaving the front for signals. Intel PowerVia ships on 18A; TSMC's version, Super Power Rail, comes with A16 in 2027. The wiring side is covered on Back-End-of-Line (BEOL).
- Complementary FET (CFET), which stacks the n-type and p-type transistors on top of each other, is in research at imec and the major foundries and is not on any announced production roadmap before 2030.
Lithography
One Company Makes Every EUV Scanner
| Generation | Maker | Where it is used |
|---|---|---|
| DUV immersion, 193nm | ASML (most), Nikon; Canon in dry DUV | Mature nodes everywhere; down to 7nm-class and 5nm-class with multi-patterning, which is how SMIC builds N+2 and N+3 |
| EUV, 0.33 numerical aperture | ASML only (NXE:3800E) | All competitive 7nm and below production; 44 systems shipped in 2025, about 65 planned for 2026; not exportable to China |
| High-NA EUV, 0.55 numerical aperture | ASML only (EXE:5200B) | Intel plans it for 14A; TSMC says A13 and A12 will not need it |
ASML is the only company that builds EUV scanners, and its output sets how fast leading-edge capacity can grow anywhere. TSMC's decision to build A13 and A12 without high-NA EUV leaves Intel as the main production customer for ASML's newest tool. Tool detail is on Lithography Equipment and ASML EUV Scanner.
Foundry roadmaps
TSMC Leads Volume; Intel Leads Backside Power
| Node | Transistor and lithography | Status, October 2026 | Products |
|---|---|---|---|
| TSMC N3 family | FinFET; EUV | High volume; 33% of TSMC wafer revenue in 3Q 2026 | Apple A17 to A19, NVIDIA Rubin, AMD and Qualcomm flagships |
| TSMC N2, N2P | GAA nanosheet; EUV | Volume since 4Q 2025 at Fab 20 and Fab 22; 8% of wafer revenue in 3Q 2026 | AMD EPYC Venice and 2026 mobile flagships |
| TSMC A16 | GAA plus Super Power Rail backside power | Volume moved to 2027 | Data center processors |
| TSMC A14, A13, A12 | GAA; second-generation nanosheets; no high-NA EUV planned | A14 high volume late 2028 at Fab 25; A13 and A12 in 2029 | Next-generation AI accelerators and CPUs |
| Samsung SF2, SF2P | GAA (MBCFET); EUV | SF2 volume since 4Q 2025, yield above 50% reported in January 2026; SF2P next | Exynos 2600 in Galaxy S26; Tesla AI5 and AI6 |
| Intel 18A, 18A-P | GAA (RibbonFET) plus PowerVia | High volume, about 30,000 wafers a month reported; 18A-P in risk production | Panther Lake; external foundry customers on 18A-P |
| Intel 14A | GAA plus PowerVia; high-NA EUV | External risk production 2028, high volume 2029 | Intel and foundry customers |
| SMIC N+3 | FinFET; DUV multi-patterning, no EUV | In production; confirmed in Huawei Kirin 9030 by TechInsights, December 2025 | Huawei only; China domestic |
| Rapidus 2nm | GAA, developed with IBM; EUV | Pilot line in Chitose since 2025; volume about 2027 | No named customers |
Revenue by node
2nm Reached 8% of TSMC Revenue in Two Quarters
TSMC's own revenue shows how fast the leading edge has become the business. In the third quarter of 2026, nodes at 7nm and below were 79% of its wafer revenue, and 2nm was already 8% two quarters after its first wafer revenue.
TSMC's share of all foundry revenue was 72.5% in the second quarter of 2026 (TrendForce), and its share at the leading edge is higher still. Samsung and Intel together ship a small fraction of TSMC's leading-edge volume to outside customers.
US leading edge
Two US Sites Make Leading-Edge Logic Today
The US makes leading-edge logic at two sites today: Intel's 18A at Fab 52 and TSMC's N4 at Fab 21. The first US 3nm wafers are due from TSMC Arizona in 2027, and US 2nm-class foundry volume depends on Samsung Taylor's ramp and TSMC's third Arizona phase.
- Made in US
- US planned
- Made abroad
| Site | Location | Makes | Status | US status |
|---|---|---|---|---|
| Intel Fab 52 | Chandler, AZ | Intel 18A | Operating | Made in US |
| Intel D1X | Hillsboro, OR | 18A-P risk production; 14A development on high-NA EUV | Operating | Made in US |
| TSMC Fab 21 phase 1 | Phoenix, AZ | N4 | Operating | Made in US |
| Samsung Taylor | Taylor, TX | SF2 for Tesla | Ramping | US planned |
| TSMC Fab 21 phase 2 | Phoenix, AZ | N3 | Production 3Q 2027 | US planned |
| TSMC Fab 21 phase 3 | Phoenix, AZ | N2 and A16 | Construction, later this decade | US planned |
| Intel Ohio | New Albany, OH | 14A and later | Construction; operations 2030 to 2031 | US planned |
| Placeholder: remaining US leading-edge rows from the fab dataset | ||||
Mature nodes and China
Most Chips Still Come From 28nm and Above
Nodes of 28nm and above make most of the chips shipped by unit count: automotive and industrial microcontrollers, power management, analog, RF, display drivers and sensors. The 2021 to 2023 shortage that stopped car lines was a mature-node shortage. 28nm is the boundary of China's self-sufficiency push and the node every major foundry, including SMIC and Hua Hong, can make at volume. See Mature-Node Logic Fabs.
US export controls bar EUV scanners and the most capable DUV immersion scanners from China, along with advanced etch, deposition and inspection tools and leading AI chips. SMIC's answer is DUV multi-patterning: N+2 is 7nm-class and N+3 is 5nm-class, both made without EUV at higher cost and lower yield than TSMC's equivalents. TechInsights found N+3 meaningfully denser than N+2 but well short of TSMC and Samsung 5nm. The wider picture is on China Bifurcation.
Record
Page Record
- Covers
- Node naming, transistor architectures, lithography generations, foundry roadmaps, TSMC revenue by node, US leading-edge sites, mature nodes and export controls
- Sources
- TSMC 3Q 2026 results (October 15, 2026); TrendForce (TSMC roadmap, April 2026; foundry share, 2Q 2026); Tom's Hardware (Intel 18A details; TSMC fab roadmap, June 2026); TechSpot citing BlueFin Research (Intel 18A, July 2026); SamMobile citing ZDNet Korea (Samsung SF2, January 2026); TechInsights (SMIC N+3, December 2025); TechSpot (Rapidus, April 2026); ASML via Crypto Briefing (EUV units, July 2026); SemiconductorX fab dataset (October 2026)
- Last verified
- October 2026