Back-End Assembly (Overview)

Back-end assembly is the traditional-packaging half of stage 3 in the manufacturing flow. It is where a tested, sorted wafer becomes a population of individually packaged, tested integrated circuits ready for board-level assembly. The other half of back-end — advanced packaging — covers 2.5D and 3D integration for chiplet-based and heterogeneous designs. This page covers the traditional assembly flow that still ships the majority of semiconductor units by volume: every wire-bonded MCU, every flip-chip BGA CPU, every encapsulated analog IC, every QFN-packaged power management device.

Traditional assembly accounts for approximately 10 to 20 percent of total semiconductor manufacturing cost, but its strategic significance has grown as packaging has become a lever on system performance and as supply concentration at specific equipment categories has tightened. The concentration story for this sub-hub is at the equipment layer: Disco dominates saw dicing; Kulicke & Soffa leads wire bonding; ASMPT and BESI dominate die attach and flip-chip bonders; Towa and ASMPT dominate encapsulation molding presses. The assembly itself is performed either captively by IDMs or outsourced to the OSAT oligopoly (ASE, Amkor, JCET, PTI, plus the Chinese OSATs Tongfu and Tianshui Huatian) — see OSAT landscape for the full operator view.

The Assembly Flow (Die to Package)

Traditional assembly runs as a short, sequential flow — typically one to two weeks from wafer arrival to packaged, tested part ready for shipment. Each step happens once per die or once per package; unlike front-end, there is no layer-build loop. The sequence below is the canonical path for wire-bonded and flip-chip packages. Advanced packaging architectures add interposer construction, multi-die bonding, and TSV processing between die attach and encapsulation, covered in Advanced Packaging.

Die Preparation

Die preparation begins the moment a sorted wafer arrives at the assembly floor. Three sub-steps: wafer thinning (also called backgrind), dicing, and cleaning. Thinning reduces the wafer to its target final thickness — typically 50 to 200 µm for standard packages, thinner for 3D stacking where TSV exposure is required. Thinning is performed on dedicated backgrind tools (Disco, Accretech, Okamoto). Dicing separates the wafer into individual dies using one of three technologies: mechanical saw dicing (the dominant mode, with Disco holding the majority share), laser dicing (for advanced or thin wafers where saw stress is a concern), and plasma dicing (for stress-free separation at advanced nodes, a growing specialty). Post-dicing cleaning removes saw debris and prepares the die surface for bonding.

Die preparation equipment concentrates at Disco (saw dicers, grinding wheels, dedicated thinning tools), Accretech (Tokyo Seimitsu) as the primary alternative source, and ASMPT as a broader packaging equipment supplier with dicing capability. Specialty plasma dicing equipment comes from Plasma-Therm and Oxford Instruments. Yield sensitivity during die preparation is high — a mishandled die is a directly lost die — which is why OSAT cleanrooms for this step are held at Class 1000 or better.

Die Attach

Die attach bonds the separated die to its package substrate, leadframe, or interposer. The bonding medium varies by application and by thermal/electrical requirements. Epoxy adhesives dominate by volume and serve most wire-bonded parts. Eutectic solder die attach provides higher thermal conductivity for power devices and performance parts. Silver sintering is used for high-reliability automotive power modules and SiC devices. Film die attach (die-attach film, DAF) is used for thin stacked dies and MCMs. Die attach equipment is high-throughput — modern die bonders place thousands of dies per hour — and concentrates at ASMPT, BESI, and Kulicke & Soffa.

Die attach materials supply is a specialty chemicals layer: Henkel, Nagase ChemteX, and Shin-Etsu dominate epoxy adhesives. Indium Corporation and Alpha Assembly Solutions (now part of MacDermid Alpha) supply solder preforms and sintering pastes. The die attach material is chosen for each package based on thermal performance, cost, and reliability requirements under end-use conditions.

Interconnect: Wire Bond vs. Flip-Chip

Interconnect is how the die's pads connect to the package. The two traditional modes are wire bonding and flip-chip; they solve the same problem with very different tradeoffs.

Wire bonding uses a fine metal wire (gold, copper, or aluminum) to connect each die pad to a lead or pad on the package. Wire bond is the lower-cost option, handles lower pin counts well, tolerates mature packaging technologies, and is the dominant mode for MCUs, analog ICs, power devices, and anything shipping at cost-sensitive volumes. Kulicke & Soffa leads the wire bonder market with ASMPT as the primary alternative. Copper wire has largely displaced gold at the mid-volume tier for cost reasons, though gold persists in high-reliability and RF applications. Copper wire bonding requires tighter process control (copper oxidizes faster than gold) but delivers similar reliability at lower material cost.

Flip-chip inverts the die and connects it via solder bumps directly to the substrate underneath. Flip-chip provides much higher pin count, lower inductance, and shorter signal paths — properties required for CPUs, GPUs, FPGAs, high-speed networking ICs, and any performance-driven SoC. Flip-chip bonders come from BESI, ASMPT, and Shinkawa. The solder bumping step itself (depositing the bumps on the wafer) is performed at the foundry (TSMC, Samsung) or at advanced OSATs (ASE, Amkor, JCET) rather than at the assembly line. Flip-Chip Bonding and Wire Bonding cover each mode in full.

Hybrid bonding — the copper-to-copper direct bond at sub-10 µm pitch that is replacing solder for 3D IC, HBM stacking, and chiplet-on-chiplet integration — is covered under Advanced Packaging. It is not a traditional interconnect mode and is included here only as a reference point.

Encapsulation & Molding

Encapsulation protects the die and its interconnects from mechanical, thermal, and environmental stress. The dominant encapsulation method for traditional packages is transfer molding: a panel of leadframes or substrates with dies attached is placed into a multi-cavity mold, and an epoxy molding compound (EMC) is heated and pressed into the cavities to form the molded package body. Compression molding is used for some higher-precision or thinner applications. For flip-chip packages, capillary underfill is applied before or after molding to fill the gap between die and substrate and redistribute thermal and mechanical stress across the solder bump array.

Molding equipment concentrates at Towa (the leading supplier globally), ASMPT, and Yamada. Epoxy molding compound supply is a specialty chemicals layer dominated by Sumitomo Bakelite, Nagase ChemteX (with its Panasonic heritage), Hitachi Chemical (now Resonac), and Kyocera. Underfill materials come from Henkel, Namics (Resonac), and specialty suppliers. Molding compound formulation is chemistry-specific to package type and end-use (automotive-grade compounds are engineered for temperature cycling; high-speed package compounds for low dielectric constant; thin-package compounds for low warpage).

Final Test

Final test is the last quality gate before a packaged part ships. Each packaged part is inserted into a test socket by a handler, connected to an automated test equipment (ATE) platform, and exercised against functional, parametric, and often stress test vectors. Defective parts are sorted out; passing parts are binned by performance grade. For automotive (AEC-Q100), medical, and mil-spec parts, final test may include burn-in — extended stress at elevated temperature to force early-life failures to surface before shipment.

Final test equipment is a three-part stack similar to wafer sort but adapted for packaged parts: handlers (Cohu, Advantest, Chroma ATE) that load packaged parts into test sockets, test sockets (a specialty consumable provided by multiple smaller vendors including Yamaichi, Ironwood, and JF Technology), and ATE platforms — Advantest for memory and high-end SoC, Teradyne for logic. Test cost per part has become a significant economic variable as test time grows with SoC complexity; test-time optimization is a major engineering focus at all high-volume assembly operations.

Traditional Package Types

Traditional packaging produces dozens of standardized package types, each optimized for a combination of pin count, electrical performance, thermal dissipation, and board-assembly cost. A few package families dominate by unit volume.

Yield, Cost & Cycle Time

Three operational variables define the economics of traditional assembly: package yield, cost per device, and cycle time. Package yield at traditional assembly is typically high — mature-process assembly lines routinely achieve 99%+ yield because the underlying steps (dicing, die attach, wire bond, molding) are well-understood and the die itself has already been sorted at wafer test. Yield losses come primarily from handling damage, wire bond failures, and molding defects, each addressable through process tuning and equipment maintenance. Advanced packaging yield is a different story — large-interposer 2.5D packages typically target 95%+ yield but run below that in ramp phases, as covered in the Advanced Packaging sub-hub.

Cost per device at traditional assembly is a small fraction of total chip cost for high-volume parts (cents per device for high-volume MCUs in QFN) but becomes significant for complex FCBGA and advanced packages (dollars to tens of dollars per package). Test cost per device is rising with SoC complexity — modern SoC final test can consume more total time than all the assembly steps combined. Cycle time from wafer arrival to finished, tested part is typically one to two weeks at OSATs running mature processes; advanced packaging programs with interposer build, hybrid bonding, and module test extend this substantially.

OSAT Operations

The Outsourced Semiconductor Assembly and Test (OSAT) industry is where most of the world's traditional assembly actually happens. OSATs are contract manufacturers that provide assembly and test services to fabless semiconductor companies (which have no fab and no back-end) and to IDMs that outsource some or all of their packaging to manage capacity and cost. The top three OSATs — ASE, Amkor, and JCET — together hold more than 60% of global OSAT revenue. Powertech Technology (PTI), Tongfu Microelectronics, Tianshui Huatian, ChipMOS, and a long tail of smaller specialty OSATs serve the rest of the market. Full operator detail is at OSAT Landscape.

OSATs cluster geographically. Taiwan is home to ASE (the global leader by revenue), PTI, ChipMOS, and SPIL (now part of ASE). China hosts JCET, Tongfu, and Tianshui Huatian. Malaysia, Philippines, Vietnam, and Thailand host Amkor satellite sites and many second-tier OSATs for cost-sensitive programs. South Korea hosts captive Samsung and SK hynix packaging plus Amkor Korea. The United States has historically hosted limited OSAT capacity; Amkor's Arizona site under construction is the flagship CHIPS Act-era reshoring project for packaging.

Related Coverage

Parent: Back-End Assembly & Packaging Hub

Sibling sub-hub: Advanced Packaging

Back-end children: Dicing · Die Attach · Bonding Overview (Wire · Flip-Chip) · BEOL Materials · Encapsulation · Final Test

OSAT & test: OSAT Landscape · Wafer Test (Sort)

Cross-pillar dependencies: Bottleneck Atlas