Wafer Test (Sort)

Wafer sort is the second segment of the four-segment manufacturing flow. Every die on a completed wafer is electrically tested before the wafer is diced. Defective dies are marked; functional dies are binned by performance (speed, power, leakage). The output is a wafer map — the data record that tells back-end assembly which dies to package and which to discard.

Sort is the first economic gate in the flow. A wafer that completes front-end fabrication carries 500 to 1,000 process steps of accumulated cost; testing defective dies out before packaging prevents that cost from compounding further through dicing, die attach, and packaging. The concentration story on this page is in the equipment stack: the automated test equipment (ATE) market is an Advantest–Teradyne duopoly, probe card supply is a tightening three-vendor oligopoly, and advanced packaging (chiplets, HBM stacks, CoWoS) is turning sort from a yield screen into a known-good-die (KGD) qualification gate that every downstream package depends on.

How Wafer Sort Works

The wafer arrives at sort in a FOUP from the front-end fab. A prober loads the wafer onto a chuck, aligns it, and steps a probe card across the wafer so that spring-loaded probe needles make temporary electrical contact with each die's bond pads or bumps. An ATE drives test vectors through the probe card into the die, measures the response, and returns pass/fail plus parametric data. The prober indexes to the next die. A modern 300mm wafer with thousands of dies is sorted in one to several hours depending on die count, test complexity, and parallelism (how many dies can be probed simultaneously).

Wafer sort runs in Class 100–1000 cleanrooms — less stringent than front-end fabrication because the wafer surface is already sealed. Vibration control is critical to maintain stable probe-to-pad contact at micron-scale alignment. Thermal chambers are used when the device must be characterized across operating temperature, which is mandatory for automotive and military-grade parts. Output is a binary map of good/bad dies plus a performance-bin map that downstream assembly uses to route dies into performance-graded packages (e.g., which dies go into high-speed CPU parts versus standard-speed parts).

Test Equipment Stack

Wafer sort runs on a three-part equipment stack. Each layer has its own vendor concentration profile; the combined stack is one of the most supply-constrained pieces of the entire semiconductor capital equipment ecosystem.

Advantest and Teradyne together hold approximately 95% of the global ATE market. Advantest dominates memory test (DRAM, NAND, HBM) and high-end SoC test; Teradyne dominates logic test for consumer, automotive, and mobile SoCs. The split is structural rather than negotiated — memory and logic test platforms have diverged enough over two decades that neither vendor cost-effectively crosses into the other's primary domain at scale.

Probe Card Supply Concentration

Probe cards have become a binding supply constraint as node advancement drives pad pitch below 40 micrometers and signal frequencies into the multi-gigahertz range. The probe card for a leading-edge AI accelerator can cost several hundred thousand dollars, must be custom-engineered per die design, and has a wear lifetime measured in the hundreds of thousands of touchdowns. The tier-1 supplier base is three companies: FormFactor (U.S.), Micronics Japan (MJC), and Technoprobe (Italy). Below that tier, Japan Electronic Materials (JEM), Korea Instrument, and several Chinese domestic suppliers cover mid-range and legacy probe card demand.

Known-Good-Die Testing for Advanced Packaging

When a chip is sold as a single packaged die, a sort miss (a bad die that escapes to packaging) costs the price of a package plus the lost die. When a chip is a multi-die module — an AI accelerator with eight HBM stacks on a CoWoS interposer, a chiplet-based CPU with nine compute tiles — a single bad die in any position scraps the entire module. A $30,000 CoWoS package built on one failed die is a catastrophic yield event. Known-good-die (KGD) testing is the response: more thorough sort coverage, tighter parametric windows, and in some cases burn-in at the wafer level to surface latent defects before the die is committed to an advanced package.

KGD pressure is reshaping sort economics. Test coverage on dies destined for CoWoS, Foveros, or 3D IC stacks now routinely exceeds what was standard for packaged-die sort five years ago. Sort time per wafer has grown accordingly. This is one of the reasons probe card supply has tightened: each KGD sort pass requires a probe card, wear accumulates faster with more touchdowns per die, and demand has grown faster than the tier-1 three can ramp capacity.

Node-Driven Complexity

Wafer sort difficulty scales with node advancement along three independent axes. Pad pitch shrinks, driving probe needle geometries below what mechanical probing can reliably achieve and forcing MEMS-based probe card construction. Signal frequencies rise into the multi-gigahertz range for AI accelerators and HBM interfaces, requiring impedance-controlled probe paths. And test vector counts grow with design complexity, extending sort time per die and driving the industry toward massively parallel test (probing 256 or more dies simultaneously) as the throughput response.

Test Data & Process Control Loop

Sort data is not just a pass/fail record. Parametric results (speed, leakage, supply current, gain) feed back into fab process control systems, where they serve as the ground-truth measurement that validates or contradicts in-line metrology. Yield learning — identifying which in-fab process variables drive which test failures — is driven from sort data. AI and machine-learning analytics applied to sort data are the basis for most modern yield-ramp programs at leading-edge foundries.

This feedback loop is why sort is increasingly performed in-fab rather than at an OSAT, particularly for leading-edge nodes. In-fab sort shortens the feedback latency from weeks to hours, enabling faster yield ramp. For mature-node, high-volume, cost-sensitive parts, OSAT-based sort remains the norm — the test equipment capital is amortized across more customers and the latency tradeoff is acceptable.

Where Wafer Sort Happens

Sort splits across two operator categories. In-fab sort is performed by the front-end fab operator (TSMC, Samsung, Intel, SK hynix, Micron, GlobalFoundries) and is standard for leading-edge logic and memory where yield-ramp feedback matters. OSAT-based sort is performed by outsourced assembly and test providers (ASE, Amkor, JCET, SPIL, PTI) and is standard for mature-node and high-volume parts where cost amortization dominates.

Related Coverage

Parent: Manufacturing Flow Hub

Peers in flow: Front-End Fabrication · Back-End Assembly & Packaging · Module Integration

Related test & equipment: Final Test · Advanced Packaging Test · WFE Hub · Process Control · AI in Fabs

Cross-pillar dependencies: HBM · CoWoS · 3D IC (KGD consumers) · Bottleneck Atlas