EDA Tools

Concentration

Two US Companies Sell Most of the Software Every Chip Needs

Electronic design automation (EDA) software turns a chip architect's description of logic into the layout file a mask shop prints. Two American companies sell most of it. Synopsys reported about $7.1 billion of revenue for fiscal 2025, which includes Ansys, the simulation company it bought for about $35 billion, from July 2025; it guides $9.69 billion to $9.74 billion for fiscal 2026. Cadence reported $5.297 billion for 2025, up 14%, and guides $5.9 billion to $6.0 billion for 2026. Siemens EDA, the former Mentor Graphics, is third and does not report its revenue separately.

The ESD Alliance, the industry body that tracks the market, counted about $21 billion of design software and design IP revenue across the four quarters of 2025 (computed from its quarterly releases). That is small against the chips it produces: the top 10 fabless companies alone sold more than $359 billion. No chip at any node reaches a foundry without passing through these tools.

The flow

US Tools Lead Every Stage; China Has No Production Synthesis or Place and Route

Vendors

Synopsys, Cadence and Siemens EDA, Then a Long Gap

The 2025 cutoff

Six Weeks of License Letters Stopped New Design Software Sales to China

In late May 2025 the US Commerce Department's Bureau of Industry and Security (BIS) sent letters requiring Synopsys, Cadence and Siemens EDA to obtain licenses for sales to China. All three suspended new sales and some support. After the June trade framework between Washington and Beijing, BIS rescinded the requirement: Synopsys announced the change on July 2 and Siemens confirmed it on July 3. The episode lasted about six weeks and showed that a few letters to three companies can halt new chip design work in the world's second-largest chip market. It also accelerated Chinese spending on domestic tools.

Separate rules still apply. Chinese firms on the Entity List, including Empyrean itself and many chip designers, need licenses for US software, and tools for gate-all-around transistor design have been controlled since 2022. Cadence's earnings releases list its China business as a risk tied to that July 2025 settlement.

China

China's Own Tools Cover Analog Far Better Than Digital

China's domestic tools cover analog and mature-node work far better than leading-edge digital design. An industry report from 2026 puts China's overall use of domestic EDA at about 15% to 20%, near 35% for analog and below 15% for digital; the two stages that decide a digital chip's speed and area, synthesis and place and route, have no domestic tool ready for production. Empyrean earned about RMB 1.32 billion in 2025, about 3.5% of Cadence's revenue. Primarius (device models), Semitronix (yield and test chips), X-Epic and Univista (verification) fill other parts of the flow. These shares are estimates, not audited figures.

AI in EDA

AI Features Run on the Incumbents' Engines

EDA vendors are adding machine learning and AI agents to search design options that engineers once tuned by hand: Synopsys DSO.ai and its AgentEngineer agents, Cadence Cerebrus and its JedAI data platform, and Siemens Solido. They are sold as faster closure on timing, power and area, and as a way to staff more designs with the same engineers. The tools run on top of the same core engines, so they deepen the dependence on the three incumbents rather than lowering it.

Related coverage

Related Coverage

• Fabless Chip Design
• IP Licensing
• Process Design Kits
• Photomasks and Reticles
• Spotlight: China Bifurcation
• Supply Chain Overview