Huawei / HiSilicon Supply Chain Spotlight

Huawei and its semiconductor design subsidiary HiSilicon are the defining case study in the global semiconductor bifurcation. No other company's supply chain story more comprehensively illustrates how export controls, domestic industrial policy, and geopolitical competition interact to restructure the semiconductor supply chain in real time. HiSilicon was, until 2020, the world's fastest-growing fabless semiconductor company - designing leading-edge SoCs manufactured at TSMC that were competitive with Apple Silicon and Qualcomm. The US export control action of May 2020, which required any company using US technology (including TSMC's manufacturing tools) to obtain a license before supplying HiSilicon, severed that relationship and forced HiSilicon to rebuild its entire supply chain around SMIC - China's leading domestic foundry that lacks EUV lithography access and operates behind US-imposed equipment restrictions.

The Huawei/HiSilicon story matters for SX because it is simultaneously three supply chain narratives running in parallel. First, it is the most concrete demonstration of what export controls actually achieve and what they do not - the Kirin 9000S in the Huawei Mate 60 Pro (2023) proved that SMIC could produce 7nm-equivalent chips without EUV, which was widely considered impossible, and validated the commercial-foundry-without-EUV thesis that China's domestic semiconductor program depends on. Second, the Ascend AI accelerator program is Beijing's mandated alternative to NVIDIA for all Chinese AI infrastructure - making Huawei/HiSilicon the demand anchor of China's entire domestic AI chip ecosystem. Third, the HBM dependency exposed by Ascend production scaling illustrates that semiconductor self-sufficiency cannot be achieved at the chip level alone - it requires domestic memory, domestic equipment, and domestic software ecosystems that China is building but has not yet completed.

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Huawei / HiSilicon at a Glance — Supply Chain Snapshot (2026)

The 2020 Export Control Inflection — How HiSilicon Was Cut Off

The US export control action of May 15, 2020, amended the Foreign Direct Product Rule to require a license before any company using US semiconductor manufacturing equipment, software, or IP could supply HiSilicon or Huawei. Since TSMC uses US-origin lithography equipment from ASML (which contains US-origin technology), Applied Materials, Lam Research, and KLA at every process node, the practical effect was immediate: TSMC could no longer manufacture chips for HiSilicon without a US government license, and licenses were not forthcoming. HiSilicon's design tape-outs at TSMC stopped. The HiSilicon Kirin 9000 - manufactured at TSMC 5nm and launched in the Huawei Mate 40 in October 2020 - was the last HiSilicon chip produced at TSMC under normal commercial terms. After September 2020, HiSilicon had no mainstream foundry.

What happened next was widely predicted to be catastrophic for Huawei's device business and is instead the most instructive case study in semiconductor supply chain resilience under pressure. Between 2020 and 2023, HiSilicon redesigned its chip supply chain around SMIC - China's largest foundry, which operates under its own US restrictions but at a different severity level than HiSilicon. SMIC does not have access to advanced EUV lithography (ASML EUV export to China was blocked by Dutch government in coordination with US policy). But SMIC had access to advanced DUV immersion scanners (ASML NXT series) acquired before the tightening controls, and SMIC's engineers developed an aggressive multipatterning process - printing each layer multiple times with DUV rather than once with EUV - that achieved approximately 7nm-equivalent transistor density. When Huawei's Mate 60 Pro launched in August 2023 with the Kirin 9000S manufactured at SMIC N+2, TechInsights teardowns confirmed what many had doubted: SMIC had achieved 7nm-class production at commercial volume without EUV. This was not a breakthrough that invalidated EUV export controls - SMIC's DUV-multipatterned 7nm is less dense, less power-efficient, and lower-yielding than TSMC N7 EUV - but it proved the commercial foundry-under-sanctions thesis and validated China's domestic semiconductor investment at the most important strategic inflection point in the bifurcation story.

The sanctions violation dimension adds an important analytical layer. TechInsights teardowns of Ascend 910B and 910C chips found that essentially every sample examined contained dies manufactured at TSMC's 7nm node - not SMIC. Huawei acquired approximately 2.9 million TSMC 7nm dies through Sophgo, a Cayman Islands-registered chip design company, in what US authorities determined was a sanctions evasion scheme. TSMC was fined $1 billion for this violation. The die bank allowed Huawei to ship meaningful Ascend volumes through 2024-2025 while SMIC's own Ascend production ramped. As of early 2026, the TSMC die bank is effectively exhausted - future Ascend production depends entirely on SMIC wafers and domestic packaging with CXMT HBM. This transition from TSMC-die-bank-supported production to fully-domestic production is the most important near-term inflection point in the Ascend supply chain.

Ascend — China's Mandated NVIDIA Alternative

The Ascend AI accelerator program is the strategic center of HiSilicon's post-sanctions rebuild. Beijing has made the Ascend ecosystem the mandatory domestic AI chip alternative to NVIDIA for state-affiliated enterprises, research institutions, and AI infrastructure build-out. The September 2025 directive to stop purchasing NVIDIA GPUs, combined with the April 2025 H20 export ban (which eliminated the last legal NVIDIA product available to Chinese buyers), has created a captive domestic market for Huawei Ascend that does not depend on competitive performance parity with NVIDIA. Chinese AI companies can complain about CANN's immaturity compared to CUDA, and they do - but they cannot legally buy NVIDIA's current generation chips, and they have government pressure to use domestic alternatives regardless.

The Ascend 910C and CloudMatrix 384 represent the current state of the art in Chinese AI compute. The 910C individually delivers approximately 60% of H100 inference performance (per DeepSeek's published assessment) - a meaningful gap but not an insurmountable one for inference tasks where model efficiency matters as much as raw compute. The CloudMatrix 384 system - 384 Ascend 910C chips interconnected through an all-to-all topology with Huawei's proprietary interconnect - achieves approximately 300 PFLOPs of dense BF16 compute, roughly double the NVL72 aggregate throughput. The critical trade-off is power: CloudMatrix 384 draws approximately 560kW versus NVL72's 145kW - 4.1 times more power for 1.7 times more compute. In China's infrastructure context, where government-backed energy allocation to AI compute is policy-supported and energy costs are subsidized for priority industries, this power inefficiency is commercially manageable in ways it would not be for US hyperscalers constrained by grid capacity and PPA costs.

The Ascend 950PR (Atlas 350) announced in 2026 represents a significant architecture advance even while remaining at SMIC 7nm. At 1.56 PFLOPS FP4 with Huawei's proprietary HiBL 1.0 memory delivering 1.4 TB/s bandwidth, it achieves 2.8x the H20's FP4 performance - making it the most capable chip available to Chinese AI buyers by a wide margin since the H20 was banned. The decision to use a monolithic die design rather than multi-chiplet is strategically significant: avoiding chiplet MCM design eliminates dependency on TSMC's CoWoS packaging technology (which Huawei cannot access) while simplifying production at SMIC. The 600W power draw is high but acceptable for the performance delivered. ByteDance's commitment of $5.6 billion in Ascend 950PR orders represents the largest single disclosed domestic AI chip procurement in China's history and validates the Ascend ecosystem beyond government-mandated adoption toward genuine commercial preference for at least some workloads.

HBM — The Binding Constraint on Ascend Production

The most important supply chain fact about Huawei's Ascend program that is consistently understated in mainstream analysis is that HBM - not SMIC wafer capacity - is the binding constraint on how many Ascend chips China can produce. SMIC's advanced node capacity (approximately 50,000 WSPM at 7nm class by end 2025) is sufficient to produce die for over one million Ascend units per year. But each Ascend chip requires HBM memory stacks - complex multi-layer DRAM packages with through-silicon vias (TSV) that require specialized manufacturing equipment not available to Chinese memory producers. Without HBM stacks to complete the package assembly, SMIC-fabricated Ascend compute dies cannot be shipped as finished products.

China accumulated approximately 13 million HBM stacks - primarily from Samsung - before export controls and the September 2025 Beijing directive tightened controls on HBM exports to China. This stockpile supported Ascend production through 2024-2025. CXMT (ChangXin Memory Technologies), China's leading DRAM company, is developing domestic HBM but is projected to produce only approximately 2 million HBM stacks in 2026 - sufficient for approximately 250,000-300,000 Ascend 910C-equivalent packages. The arithmetic is stark: SMIC can produce die for more than one million Ascend chips per year, but domestic HBM supply constraints production to under 300,000 units without stockpiled foreign HBM. If Samsung HBM supply to China is effectively closed and CXMT's ramp proceeds as projected, Ascend production in 2027 may be constrained to CXMT output even as SMIC wafer capacity is underutilized.

The CXMT HBM program is the most strategically important domestic semiconductor development project in China that is not Huawei/HiSilicon itself. CXMT is expanding aggressively - Hefei facility, Shanghai expansion, Beijing expansion, HBM packaging subsidiaries - backed by China's Big Fund III ($2B investment). Its roadmap claims HBM3e production capability in 2026, which if achieved at meaningful volume would substantially relieve the Ascend production constraint. The catch is that HBM manufacturing requires specialized equipment from the same Western suppliers (Applied Materials, Lam Research, Tokyo Electron) that are subject to export controls for advanced process tools. CXMT has stockpiled equipment ahead of tightening controls, but its ability to sustain HBM capacity expansion without continued Western equipment access is the unresolved question that determines whether China can achieve AI compute independence at meaningful scale.

CANN vs CUDA — The Software Moat

The semiconductor performance gap between Ascend and NVIDIA's current generation is meaningful but quantifiable - Ascend 950PR at 1.56 PFLOPS FP4 versus NVIDIA Blackwell's 20 PFLOPS FP4 represents approximately a 13x raw compute gap at the chip level. What is harder to quantify and substantially larger as a competitive barrier is the CUDA software ecosystem gap. CUDA has been the programming model for GPU-accelerated computing since 2006 - almost two decades of library development, framework optimization (PyTorch, TensorFlow, JAX all have CUDA as their native backend), model optimization tools (TensorRT, cuDNN), and millions of developer-years of workflow investment. The CUDA ecosystem means that a deep learning researcher trained anywhere in the world knows how to use NVIDIA hardware efficiently; using Ascend with CANN requires learning a new programming model, re-optimizing models that were tuned for CUDA assumptions, and dealing with a library ecosystem that is a fraction of CUDA's depth.

Huawei's response to the CUDA moat is threefold. First, CANN provides PyTorch adapters that allow models written for CUDA to run on Ascend without complete rewriting - the adaptation is imperfect and loses some performance, but it dramatically lowers the migration barrier. Second, Huawei announced in 2025 that CANN, MindSpore (its deep learning framework), and Pangu (its foundation model series) would all go open-source, creating an external developer community with incentive to build on Ascend. Third, the government mandate means Chinese AI companies are developing native CANN workflows regardless of comparative efficiency, creating a domestic CUDA-equivalent developer base over time. DeepSeek's ability to achieve NVIDIA H100-class results with less compute using algorithmic efficiency demonstrates that Chinese AI labs are not simply hardware-limited - they are building algorithmic workarounds to the hardware gap that reduce the performance penalty of using Ascend for inference.

The honest assessment: CANN will not match CUDA's ecosystem depth within this decade. The developer tools, the library breadth, the framework integration, and the institutional knowledge embedded in CUDA represent an asset built over 20 years that Huawei started rebuilding from scratch in 2020. What CANN can achieve is functional adequacy for Chinese domestic AI development workflows - good enough that Beijing's mandate to use domestic hardware can be executed without completely abandoning model quality. Whether CANN becomes genuinely competitive outside China - attracting developers in South Korea, Southeast Asia, the Middle East, and other markets that are not subject to the same US-China alignment pressure - determines whether Huawei Ascend becomes a global competitive platform or a China-only necessity.

The SMIC Node Ceiling — What DUV Without EUV Actually Limits

The export control on EUV lithography is the most consequential single equipment restriction in the US-China semiconductor conflict, and understanding what it actually prevents requires precision. EUV export controls do not prevent SMIC from manufacturing at 7nm-equivalent density - the Kirin 9000S and Ascend 910B/C prove that. What EUV export controls prevent is economically competitive manufacturing below approximately 7nm density using any realistic DUV multipatterning scheme.

SMIC's N+2 process (also called 2nd Gen 7nm) achieves approximately 7nm-equivalent feature density through aggressive DUV multipatterning - printing each critical layer two, three, or four times with different mask sets to achieve feature sizes smaller than a single DUV exposure can print. This works technically but has three specific disadvantages versus TSMC EUV production. First, yield is lower because each additional mask exposure adds another opportunity for defect introduction and overlay error accumulation - more masks means more opportunities to miss alignment. Second, throughput is lower because each wafer takes more time in the scanner for the same number of functional layers, reducing effective fab output per scanner per day. Third, the process is at or near the practical ceiling of what DUV multipatterning can achieve at commercial yield - further density improvement below current SMIC N+2 requires either EUV or a new patterning approach that does not currently exist at commercial maturity. SMIC is working on SMIC N+3 (6nm class) with Huawei engineering support, and SciCarrier (a Chinese equipment startup with Huawei backing) is developing domestic lithography equipment, but neither represents a near-term path below SMIC's current DUV ceiling at high-volume commercial yield.

The practical consequence for Ascend performance trajectory: Huawei's Ascend 950PR achieves 1.56 PFLOPS FP4 at the same SMIC 7nm process as the 910C. The performance improvement over 910C comes from architectural innovation - better tensor core design, more efficient memory subsystem, improved interconnect, die size optimization - not from transistor scaling. Future Ascend generations will continue to improve through architecture while SMIC's process advances incrementally from N+2 to N+3 to potentially N+4 (5nm class). The performance trajectory is upward but bounded: Huawei engineers can extract more performance from a given process node through microarchitectural innovation, but the fundamental compute density ceiling is set by the process node, and SMIC's process node ceiling is set by the absence of EUV. This is why Huawei's own 2028 roadmap targets 4 ZettaFLOPS FP4 at system scale through large-scale cluster deployment rather than single-chip performance parity with NVIDIA's Blackwell or Rubin.

Supply Chain Bottlenecks — Huawei / HiSilicon AI Compute

Key Questions — Huawei / HiSilicon Supply Chain

Are US export controls on semiconductors working? The answer depends on what "working" means. If the objective was to prevent China from producing 7nm-equivalent chips entirely, the controls have not achieved that - the Kirin 9000S demonstrated in 2023 that SMIC can produce 7nm-class devices without EUV at commercial volume. If the objective was to prevent China from achieving performance parity with TSMC-manufactured NVIDIA AI chips, the controls are working - the 2-3 process generation gap between SMIC N+2 and TSMC N3/N2 translates directly to AI chip performance per unit area, and the HBM supply constraint limits how many Ascend units China can produce even when SMIC die supply is adequate. The controls have not prevented China from building a functional domestic AI compute ecosystem; they have constrained the pace of that ecosystem's performance improvement and limited production volumes significantly below unconstrained demand. Whether this constitutes strategic success depends on whether the primary US objective was absolute capability denial (unlikely to succeed in the long run) or pace-of-development constraint (partially succeeding).

Can China achieve AI self-sufficiency? At compute performance comparable to NVIDIA Blackwell/Rubin? No, within this decade, given EUV export controls hold. At compute performance adequate for Chinese domestic AI development and deployment? Already partially yes, and increasingly yes as CXMT HBM scales, SMIC process matures, and CANN ecosystem deepens. The DeepSeek R1 result - frontier-class AI model performance achieved with dramatically less compute than Western equivalents suggested was necessary - illustrated that algorithmic innovation can partially compensate for hardware capability gaps. China does not need parity with NVIDIA's best chips to maintain a competitive domestic AI development program; it needs adequate performance at accessible cost for the models Chinese labs are developing. Ascend 950PR at 1.56 PFLOPS FP4 with ByteDance's $5.6B commitment suggests that threshold has been reached for at least inference workloads.

What does the H20 ban mean for NVIDIA's China revenue? The April 2025 H20 ban - eliminating the last legal NVIDIA product for Chinese buyers - is the most commercially significant single export control action for NVIDIA's revenue since the initial A100/H100 restrictions. NVIDIA's China revenue fell from approximately 17% of total in FY2023 to below 10% and declining by 2025-2026, with analysts projecting further decline toward low-single-digit percentages as Ascend deployment fills the market. Jensen Huang has stated NVIDIA's China market share has effectively gone to zero for current products. The loss of China revenue - historically one of NVIDIA's largest markets - is partially offset by US, European, and Asian hyperscaler demand for Blackwell and Rubin systems that is running at a $1 trillion order backlog pace. But for NVIDIA's long-term market structure, the China bifurcation permanently removes a large market from its addressable revenue base while potentially creating a competitor (Huawei Ascend) that could eventually compete in non-China markets if export control alignment weakens.

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