Huawei / HiSilicon Supply Chain Spotlight

Huawei and its chip design subsidiary HiSilicon show more clearly than any other company how export controls have split the semiconductor supply chain. Until 2020, HiSilicon was the world's fastest-growing fabless chip company, designing leading-edge Kirin SoCs at TSMC that competed with Apple and Qualcomm. A May 2020 U.S. export rule cut HiSilicon off from TSMC, and it rebuilt its supply chain around SMIC, China's leading foundry, which has no access to extreme ultraviolet (EUV) lithography.

The Kirin 9000S in the Huawei Mate 60 Pro (2023) showed that SMIC could make 7nm-class chips without EUV, which many analysts had considered impossible. The Ascend AI accelerator line is Beijing's mandated alternative to NVIDIA and anchors demand for China's domestic AI chip industry. Ascend output in turn depends on high-bandwidth memory (HBM), equipment and software that China is still building. The country-level picture across foundry, memory, equipment and materials is on China Semiconductor Bifurcation.

Huawei and HiSilicon Supply Chain Snapshot (2026)

• HiSilicon structure: HiSilicon is China's largest domestic IC designer by revenue, designing Kirin mobile SoCs, Ascend AI accelerators, Kunpeng server CPUs, SmartNIC and switch ASICs, base station chipsets and, from 2026, camera image signal processors such as the CS520V200. Pre-2020 TSMC inventory is exhausted.
• Mobile SoC (Kirin): Kirin 9000S arrived in 2023, Kirin 9010 and 9020 in 2024 and the Kirin X90 PC chip for MateBook in 2025; Kirin 9100 (6nm class, SMIC N+3) is rumored but not confirmed in production. High-volume SMIC production stayed at N+2 through 2025 and 2026 while Apple and Qualcomm moved to TSMC 2nm.
• Ascend AI accelerator (current): The 910C pairs two 910B chiplets on SMIC N+2 with about 780 TFLOPS BF16 and 128GB HBM, the 60% figure is DeepSeek's assessment, and 653,000 of the 2025 units were 910C. CloudMatrix 384 (384 Ascend 910C chips) exceeds NVL72 aggregate compute but draws about 560kW against about 145kW, and the main customers are Alibaba, Tencent, Baidu, ByteDance and DeepSeek.
• Ascend AI accelerator (2026 roadmap): The 950PR (Atlas 350) is a 600W monolithic SMIC 7nm die that avoids CoWoS packaging, with 112GB of HiBL 1.0 proprietary memory at 1.4 TB/s and 2.8 times H20 FP4 performance; the 950DT decode and training variant carries 144GB of HiZQ 2.0 at 4 TB/s. The Atlas 950 SuperPoD (Q4 2026) puts 8,192 Ascend 950DT chips in 160 cabinets, and Huawei claims 6.7 times NVL144 compute.
• Longer-range roadmap: Ascend 920 (SMIC 6nm, 900 TFLOPS BF16, HBM3, 4 TB/s) was announced in April 2025, the day after the H20 ban, and Ascend 960 doubles Ascend 950 compute. The 2028 target is at system level, and node advances depend on SMIC 5nm and 6nm yield.
• Manufacturing dependency: N+3 (6nm class) is in development, held back by the lack of advanced deep ultraviolet (DUV) scanners and process maturity, and SMIC 5nm is in development with Huawei equipment engineering support. The TSMC die bank (2.9 million dies obtained through Sophgo) is exhausted, with no further TSMC access.
• HBM dependency: China built the stockpile, mostly Samsung, before controls tightened, and CXMT's 2026 output covers 250,000 to 300,000 Ascend 910C-equivalent packages. SMIC has wafer capacity for more than one million Ascend dies a year.
• Software ecosystem: CANN is Huawei's Ascend programming framework with PyTorch adapters, MindSpore its deep learning framework and Pangu its LLM family, and Huawei announced the open-source plan in 2025. DeepSeek R1 trained on NVIDIA H800 and runs inference on Ascend 910C.
• Policy context: The H20 ban on April 9, 2025 removed the last NVIDIA product legal to sell in China, and the September 2025 directive told government bodies and state enterprises to stop buying NVIDIA GPUs and speed up Ascend adoption. NVIDIA's China market share fell from about 66% to under 60%, and analysts project a fall toward single digits.
• 5G radio access network: Huawei dominates Asia, the Middle East, Africa and Latin America, HiSilicon designs the base station chipsets (Tiangang massive MIMO, Balong modem), and RAN revenue outside Western-aligned countries funds HiSilicon chip development.

The 2020 Export Rule and the Move to SMIC

On May 15, 2020, the U.S. amended the Foreign Direct Product Rule to require a license before any company using U.S. chipmaking equipment, software or IP could supply Huawei or HiSilicon. TSMC runs ASML, Applied Materials, Lam Research and KLA tools that contain U.S. technology at every node, so it could no longer build HiSilicon chips, and no licenses were granted. The Kirin 9000, built on TSMC 5nm for the Huawei Mate 40 in October 2020, was the last HiSilicon chip made at TSMC on normal terms. After September 2020, HiSilicon had no mainstream foundry.

Between 2020 and 2023, HiSilicon moved its designs to SMIC. The Netherlands, in coordination with U.S. policy, had blocked ASML EUV exports to China, but SMIC held ASML NXT DUV immersion scanners bought before controls tightened. SMIC engineers developed a multipatterning process that prints each critical layer several times with DUV and reaches about 7nm-equivalent density. TechInsights teardowns of the Mate 60 Pro, launched in August 2023, confirmed the Kirin 9000S was built on SMIC N+2 at commercial volume. SMIC N+2 is less dense, less power-efficient and lower-yielding than TSMC 7nm-class production, but it gave China's domestic chip program a working advanced node.

TechInsights teardowns of Ascend 910B and 910C chips found that nearly every sample contained TSMC 7nm dies. Huawei obtained about 2.9 million of them through Sophgo, a Cayman Islands-registered chip design company, in what U.S. authorities found to be sanctions evasion, and TSMC was fined $1 billion. That die bank carried Ascend shipments through 2024 and 2025 while SMIC ramped its own Ascend production. It was effectively exhausted by early 2026, so Ascend output now depends entirely on SMIC wafers, domestic packaging and CXMT HBM.

Ascend as China's NVIDIA Alternative

Beijing has made Ascend the required domestic alternative to NVIDIA for state-affiliated enterprises, research institutions and AI infrastructure. The September 2025 directive and the April 2025 H20 ban together leave Chinese AI buyers with no legal NVIDIA option, so Ascend has a captive home market whatever its performance gap. Chinese AI companies criticize CANN's immaturity next to CUDA but cannot buy NVIDIA's current chips and face government pressure to use domestic hardware.

The Ascend 910C delivers about 60% of H100 inference performance, according to DeepSeek. CloudMatrix 384 links 384 Ascend 910C chips in an all-to-all topology over Huawei's proprietary interconnect and reaches about 300 PFLOPS of dense BF16 compute, about 1.7 times an NVIDIA NVL72 rack. It draws about 560kW against 145kW for NVL72, nearly four times the power. Chinese government energy allocation and subsidized power for priority industries make that penalty manageable in China, where U.S. hyperscalers face grid limits and power purchase agreement (PPA) costs.

The Ascend 950PR (Atlas 350) stays on SMIC 7nm but delivers 1.56 PFLOPS of 4-bit floating point (FP4) compute with Huawei's HiBL 1.0 memory at 1.4 TB/s, 2.8 times the H20's FP4 performance. Its monolithic die removes any need for TSMC CoWoS packaging, which Huawei cannot get, and simplifies production at SMIC. The chip draws 600W. ByteDance's $5.6 billion order is the largest disclosed domestic AI chip purchase in China and shows commercial demand for Ascend on at least some workloads, beyond government-mandated use.

NVIDIA's China revenue fell from about 17% of total in fiscal 2023 to under 10% by 2025 and 2026, and analysts project low single digits as Ascend fills the market. Jensen Huang has said NVIDIA's China share for current products is effectively zero. Hyperscaler demand for Blackwell and Rubin in the U.S., Europe and Asia, running at a $1 trillion backlog pace, offsets the loss, but Ascend could compete outside China if allied export controls weaken. NVIDIA's position is covered on the NVIDIA Spotlight.

HBM Supply Limits Ascend Output

HBM supply, more than SMIC wafer capacity, sets how many Ascend chips China can ship. SMIC's 7nm-class capacity of about 50,000 wafer starts per month (WSPM) by end of 2025 can supply dies for more than one million Ascend units a year. Each Ascend package also needs HBM stacks, multi-layer DRAM joined with through-silicon vias (TSVs), which require specialized equipment that Chinese memory makers lack, and a compute die without HBM cannot ship.

China stockpiled about 13 million HBM stacks, mostly from Samsung, before U.S. export controls cut off HBM shipments, and that stockpile carried Ascend production through 2024 and 2025. CXMT (ChangXin Memory Technologies), China's leading DRAM maker, is projected to produce only about two million HBM stacks in 2026, enough for 250,000 to 300,000 Ascend 910C-equivalent packages. If Samsung supply stays closed and CXMT ramps as projected, Ascend production in 2027 may be held to CXMT output while SMIC wafer capacity sits underused.

CXMT is expanding in Hefei, Shanghai and Beijing and through HBM packaging subsidiaries, backed by a $2 billion Big Fund III investment. Its roadmap claims HBM3E capability in 2026, which at volume would ease the Ascend constraint. HBM production depends on equipment from Applied Materials, Lam Research and Tokyo Electron, which falls under export controls. CXMT stockpiled tools ahead of the controls, but sustained HBM growth without continued Western equipment access is unproven. HBM technology is covered on HBM.

CANN and the CUDA Software Ecosystem

The Ascend 950PR delivers 1.56 PFLOPS FP4 against 20 PFLOPS for NVIDIA Blackwell, about a 13 times gap per chip. The software gap is larger and harder to close. CUDA has been NVIDIA's GPU programming model since 2006, and PyTorch, TensorFlow and JAX all use it as their native backend, alongside optimization libraries such as TensorRT and cuDNN. Moving to Ascend means learning CANN (Compute Architecture for Neural Networks), re-tuning models built around CUDA and working with a much thinner library base.

Huawei is narrowing the gap on several fronts:

• PyTorch adapters: CANN runs CUDA-targeted models on Ascend without a full rewrite, at some performance cost.
• Open source: Huawei announced in 2025 that CANN, the MindSpore framework and the Pangu foundation models would be open-sourced to build an outside developer community.
• Government mandate: Chinese AI companies are building native CANN workflows because they must, which grows a domestic developer base over time.
• Algorithmic efficiency: DeepSeek R1 reached frontier-class results with far less compute than Western labs assumed, using mixture of experts, distillation and speculative decoding, which reduces the penalty of running inference on Ascend.

CANN is unlikely to match CUDA's depth this decade, because CUDA's tools, libraries and framework integration took about 20 years to build and Huawei started over in 2020. CANN is expected to be adequate for domestic Chinese workloads within two to three years. Wider use in South Korea, Southeast Asia and the Middle East would decide whether Ascend becomes a global platform or stays a China-only product. Training models larger than today's frontier still needs raw compute that HBM-limited Ascend production cannot yet supply.

SMIC Process Limits on Ascend Performance

DUV multipatterning lets SMIC reach 7nm-class density but costs yield and scanner throughput, and further shrinks need EUV or a patterning method that is not yet commercial. The mechanism and China's domestic lithography programs are covered on China Semiconductor Bifurcation.

The Ascend 950PR runs on the same SMIC 7nm process as the 910C, so its gains come from architecture: tensor core design, the memory subsystem, interconnect and die size. Later Ascend generations will improve the same way while SMIC moves from N+2 to N+3 and possibly N+4 (5nm class). NVIDIA Blackwell (TSMC N4P) and Rubin (TSMC N3) sit two to three process generations ahead, so Huawei's 2028 target of 4 ZettaFLOPS FP4 relies on large clusters to make up for lower per-chip performance.

U.S. controls have not stopped China from making 7nm-class chips or from building a working domestic AI compute stack. They have slowed its performance gains through the process gap and held Ascend volumes well below demand through the HBM shortage.

Huawei and HiSilicon AI Compute Bottlenecks

• HBM supply: Two million stacks cover 250,000 to 300,000 Ascend packages against a Chinese build-out needing millions of accelerators a year, and Samsung and SK Hynix HBM exports to China are increasingly restricted. HBM stops limiting output if CXMT reaches five to 10 million stacks a year by 2028, which needs continued access to mostly Western equipment, and CXMT HBM3E is possible in 2026 to 2027 at uncertain volume.
• SMIC process ceiling: N+3 and N+4 need more multipatterning with lower yield and throughput, and NVIDIA Blackwell (TSMC N4P) and Rubin (TSMC N3) are two to three generations ahead. The gap widens as TSMC moves through N2, A16 and A14, and the SiCarrier and SMEE domestic lithography programs are pre-commercial.
• TSMC die bank exhaustion: About 2.9 million TSMC 7nm dies obtained through Sophgo carried Ascend 910B and 910C production through 2024 and 2025, and all-SMIC parts may differ in reliability. 2026 shipment data will show the yield and reliability of all-SMIC Ascend.
• No access to CoWoS packaging: The monolithic 950PR die also rules out the HBM integration used in NVIDIA GB200 and Rubin. Chinese outsourced assembly and test (OSAT) firms JCET and Tongfu Microelectronics are developing advanced packaging, Huawei HiBL and HiZQ memory interfaces and larger clusters partly offset the limit, and no timeline exists for a Chinese CoWoS equivalent at scale.
• CANN ecosystem immaturity: The mandate assures domestic adoption, open-source CANN and algorithmic efficiency help, and global competitiveness is a decade-scale question.
• Western equipment and consumables: SMIC and CXMT bought Western tools before controls but still need Western spare parts, calibration, process gases and photoresists from JSR, Tokyo Ohka and Sumitomo, and the risk accumulates slowly as stockpiles age without replenishment. NAURA, AMEC, SMEE and domestic chemical suppliers are advancing, and the near-term risk is tool aging and consumables (see China Semiconductor Bifurcation).

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