Four segments
The Four Semiconductor Manufacturing Segments
Front-end fabrication repeats once per layer and takes most of a fab's capital and tool variety. Test, assembly and module integration run once per unit, each with its own small group of suppliers.
| Segment | What happens | Iteration | Primary concentration |
|---|---|---|---|
| Front-end fabrication | Transistors and interconnect are built layer by layer on the wafer | 80-120 per wafer (the layer-build loop) | Wafer fab equipment (WFE): ASML, Applied Materials, Lam Research, Tokyo Electron (TEL) and KLA control more than 70% of tool spend |
| Wafer test | Probe stations test each die on the wafer electrically; defective dies are marked | Once per wafer pass | Automated test equipment (ATE): Advantest and Teradyne |
| Back-end assembly and packaging | Wafers are diced; dies are bonded, wired and encapsulated in packages | Once per die | Outsourced assembly and test (OSAT): ASE, Amkor, JCET, SPIL, PTI |
| Module integration | Packaged dies combined into chiplets, tiles, superchips, boards or wafer-scale modules | Once per module | Advanced packaging capacity: TSMC CoWoS, Intel EMIB and Foveros, Samsung SAINT |
The layer-build loop
The Layer-Build Loop in Front-End Fabrication
Every patterned layer of a chip, each transistor level, each metal wiring level and each via between them, takes at least one pass through the same six steps.
A modern logic chip has 80 to 120 such layers. The wafer passes through the loop once per layer, using about 90 photomasks and 500 to 1,000 discrete steps before it reaches wafer test. Deposition and etch change with the layer being built: gate oxide deposition uses different chemistry from copper interconnect deposition, and polysilicon etch uses a different plasma from low-k dielectric etch.
- Ion implantation and oxidation run outside the core loop, only for specific layers, mostly during transistor formation and well isolation.
- Chemical mechanical planarization (CMP) runs on most passes to flatten the wafer so the next layer can be patterned accurately, which makes it a seventh step in practice.
Step-by-step process detail, vendors and fab metrics are on Front-End Fabrication.
Layer count
Layer Count by Chip Type
Logic layer count rises with each node; 3D NAND stacks hundreds of layers vertically and is limited by high-aspect-ratio etch, not lithography.
| Chip type | Layers | Mask layers | Notes |
|---|---|---|---|
| 90nm CMOS logic | 35-50 | ~30 | Legacy, analog and MCU baseline |
| 7nm FinFET logic | 60-80 | ~70 | First widespread EUV use |
| 3nm GAA logic | 80-120 | ~90 | Gate-all-around; heavy EUV, selective multi-patterning |
| DRAM (planar) | 40-70 | ~40 | Dominated by capacitor formation |
| 3D NAND flash | 64-232+ | ~60 | Vertical stack; high-aspect-ratio etch through the stack is the bottleneck |
Front-end steps
Front-End Fabrication Steps
Front-end steps fall into surface preparation, layer building and patterning, and electrical modification and verification. Each step links to its process page and to the equipment that performs it.
- Surface preparation
- Build and pattern
- Modify and verify
| Step | Role | Iteration | Tool category |
|---|---|---|---|
| Wafer cleaning | Surface prep | Every loop pass | Wet benches and single-wafer cleaners |
| Oxidation | Grow insulating oxide | Selective (gate and isolation layers) | Thermal furnaces |
| Deposition (CVD, PVD, ALD, epitaxy) | Add film | Every loop pass | Deposition |
| Photoresist coat | Prep for patterning | Every litho pass | Coater-developer tracks |
| Photolithography (exposure) | Pattern transfer | About 90 mask layers | Lithography |
| Develop | Reveal pattern | Every litho pass | Coater-developer tracks |
| Etch (dry and wet) | Remove unprotected material | Every loop pass | Etch |
| Metallization | Build interconnect | Multi-level (BEOL stack) | Deposition plus electroplating |
| Ion implantation | Dope silicon | Selective (transistor regions) | Implanters (Applied Materials, Axcelis) |
| CMP | Planarize surface | Most loop passes | CMP |
| Metrology and inspection | Verify each layer | Every loop pass | Metrology and inspection |
Back-end and module steps
Back-End Assembly and Module Integration Steps
After front-end fabrication and wafer test, the wafer goes through fewer but more physically varied steps. Back-end assembly turns the wafer into individual packaged chips. Module integration combines packaged chips or bare dies into the multi-die builds used in AI and high-performance compute: chiplets, interposers, tiles and wafer-scale modules.
- Back-end assembly
- Module integration
| Step | Role | Iteration | Tool or facility |
|---|---|---|---|
| Wafer thinning and backgrind | Reduce wafer to target thickness | Once per wafer | Backgrind tools (Disco, Accretech) |
| Dicing | Separate wafer into dies | Once per wafer | Dicing saws, laser or plasma |
| Die attach | Bond die to substrate or leadframe | Once per die | Die bonders (ASMPT, BESI, K&S) |
| Wire bonding or flip-chip bump | Electrical connection to package | Once per die | Wire bonders and bumping lines |
| Encapsulation and molding | Protect die and leads | Once per package | Molding presses |
| Final test and burn-in | Validate packaged part | Once per package | ATE (Teradyne, Advantest) |
| Interposer and RDL build | Create multi-die routing layer (redistribution layer, RDL) | Per module | Advanced packaging lines (CoWoS, EMIB) |
| Multi-die bonding (2.5D and 3D) | Stack or tile multiple dies | Per module | Hybrid bonders (BESI and Applied Materials, TEL) |
| Module-level test | Validate assembled module | Once per module | System-level test platforms |
Wafer logistics
Wafer Logistics Inside the Fab
A wafer has no fixed path through the fab. It moves between hundreds of single-purpose tools, often from different vendors, under digital scheduling. A fab has no conveyor, no fixed sequence and no guaranteed tool-to-tool adjacency, unlike an automotive assembly line, and one wafer may visit the same etch module a dozen times with a different recipe each time.
| System | Role | Function |
|---|---|---|
| FOUP (front-opening unified pod) | Wafer carrier | Holds 25 wafers; isolates them from cleanroom air |
| EFEM (equipment front-end module) | Tool-side load port | Robotic wafer transfer between FOUP and process chamber |
| AMHS (automated material handling system) | Fab-wide transport | Overhead rail or floor vehicles move FOUPs tool to tool |
| MES (manufacturing execution system) | Digital control | Schedules every wafer, tracks recipe history, routes by queue depth |
Masks, capex and cycle time
Mask Count, Capex and Cycle Time by Node
The cost of each loop pass multiplies by the number of layers, so mask count, cycle time and line capital cost rise together as nodes advance.
Below about 7nm, multi-patterning and High-NA EUV raise mask count and step count faster than the geometric shrink. Tool cost by node is on Wafer Fab Equipment.
| Node | Mask layers | Line capex | Cycle time |
|---|---|---|---|
| 14nm / 10nm | ~55 | $2-3B | ~10 weeks |
| 7nm | ~70 | $4-6B | ~12 weeks |
| 5nm | ~80 | $6-8B | ~13 weeks |
| 3nm (GAA) | ~90 | $10-12B | ~14 weeks |
| 2nm | ~95+ | $15-20B | ~16 weeks |
| Sub-2nm | 100+ | $20B+ | 16+ weeks |
Hubs
Equipment, Facilities and Materials Hubs
The equipment, the fabs, the consumables and the upstream materials behind each step each have their own hub.
| Axis | Lens | Hub |
|---|---|---|
| Equipment | The tools that run each step | Wafer Fab Equipment |
| Facilities | The fabs and OSATs that house the tools | Fab Facilities |
| Consumables | The materials the tools apply or remove | Fab Process Consumables |
| Materials upstream | Raw substrates, gases and IP blocks feeding the flow | Materials and Process Inputs |
Record
Page Record
- Covers
- Manufacturing segments, the layer-build loop, layer and mask counts, front-end and back-end steps, wafer logistics, and capex and cycle time by node
- Sources
- Company filings and investor materials (TSMC, Intel, Samsung, ASML, Applied Materials, Lam Research, Tokyo Electron, KLA), SEMI, imec, TechInsights
- Last verified
- October 2026