Module Integration

Fourth manufacturing segment · packaged dies in, compute and power modules out

Module integration is the last manufacturing step before a chip becomes part of a system: voltage regulators, passives, connectors and cooling are added around the packaged dies. Power and heat now set the limit there. An NVIDIA GB200 superchip module draws up to 2,700 W, nearly four times an H100 SXM module's 700 W, so the regulators and cold plates added at the module decide how much compute a rack can hold.

Four layers from a logic die to a rack: the die, the package with HBM on an interposer, the module where voltage regulators and cold plates are added and an NVIDIA GB200 superchip draws up to 2,700 watts, and the server tray and rack, which DatacentersX covers WHAT EACH LAYER ADDS, DIE TO RACK Die logic die 858 MM2 RETICLE LIMIT PER DIE Package dies, HBM, interposer COWOS-L: 2 GPU DIES, 8 HBM STACKS COLD PLATE PACKAGE REGULATORS Module power and cooling GB200 SUPERCHIP: UP TO 2,700 W Rack on DatacentersX GB200 NVL72: 72 GPUS PER RACK SEMICONDUCTORX DATACENTERSX
Segment
4 of 4
GB200 module
up to 2,700 W
H100 SXM
700 W
Open chiplet standard
UCIe 3.0, 2025
Handoff
DatacentersX
Hub
Process

Where modules sit

The Last Step Before the System

Packaged dies arrive from back-end assembly and packaging; what leaves is a working unit one step below a system: a compute module, a memory stack, a power module, a phone system-in-package or a vehicle compute board.

The upstream boundary is loose. A CoWoS package with a logic die and HBM stacks on a silicon interposer is advanced packaging; the same package with its carrier, heat spreader and power delivery network is a module. Downstream, a GPU module with its HBM, regulators and connectors is still a module; a server tray holding eight of them is a system, and the server, rack and cluster are covered on DatacentersX.

The disciplines at this layer are chip-package-board co-design, power integrity, signal integrity, thermal simulation and mechanical design for warpage and stress. Each manufacturing segment before it runs once per wafer or per die; module integration runs once per module.

Module categories

Seven Kinds of Module

Module categories
CategoryWhat it isRepresentative products
Compute modules (AI and HPC)AI accelerator or CPU package with HBM and regulators on a module or carrierNVIDIA GB200 and GB300 superchips, B200 SXM; AMD Instinct MI355X OAM
Multi-chip modulesSeveral dies on a shared substrate, linked at module levelNVIDIA Grace CPU Superchip; AMD EPYC; Huawei Ascend 910C
Memory modulesDRAM or NAND dies built into stacks, DIMMs or drivesHBM3E and HBM4 stacks; DDR5 RDIMMs; CXL memory; enterprise SSDs
Power modulesIGBT, SiC or GaN switches on ceramic substratesEV traction inverter modules; solar, rail and data center power
RF modulesPower amplifiers, filters, switches and LNAs in one front-endSmartphone PAMiD modules; Wi-Fi front-ends; 5G mmWave antenna modules
Sensor modulesSensor die plus optics, mechanics and processingPhone and car camera modules; LiDAR; MEMS inertial units
System-in-package modulesLogic, memory, passives and RF sealed in one packageApple Watch S-series; earbud and wearable SiPs

Flagship modules

Flagship Modules

Reference modules, October 2026
ModuleIntegratorArchitecture
GB200 and GB300 superchipsNVIDIAOne Grace CPU and two Blackwell GPUs joined by NVLink-C2C; liquid-cooled; GB200 up to 2,700 W
Vera Rubin superchipNVIDIAVera CPU and Rubin GPUs joined by NVLink-C2C at 1.8 TB/s; Rubin carries 288 GB of HBM4; samples shipped February 2026, volume second half of 2026
Instinct MI355X OAMAMDCDNA 4 GPU chiplets with 288 GB of HBM3E; up to 1,400 W liquid-cooled; MI450 series in the Helios rack follows in 2026
Ascend 910CHuawei (HiSilicon)Two Ascend dies in one package; built into the CloudMatrix 384 system
Apple Watch S-series SiPAppleProcessor, memory, sensors and passives sealed into one module
AI5 vehicle computerTeslaAI5 chip with power delivery and connectors in an automotive enclosure; chips made by TSMC and Samsung (see Terafab)

Tesla ended its Dojo training-tile program in August 2025 and moved its engineers to the AI5 and AI6 chips, retiring the 25-die D1 tile that had served as a reference design for wafer-scale training modules.

Power delivery

Power Per Package Has Grown Nearly Fivefold Since 2017

Each NVIDIA data center GPU generation has drawn more power per package, and the module is where that current has to be delivered.

NVIDIA DATA CENTER GPU POWER, WATTS PER PACKAGE 0 600 1,200 1,800 2,400 V100 SXM2, 2017 300 W A100 SXM4, 2020 400 W H100 SXM5, 2022 700 W B200 HGX, 2024 1,000 W B300 Blackwell Ultra, 2025 1,400 W upper end Rubin 2026 2,300 W reported
Rubin power is an analyst estimate; NVIDIA has not published it.

Delivering more than 1,000 A below 1 V through a conventional board power network loses too much to resistance, so power delivery has moved closer to the die: tighter regulator placement on the module, passives embedded in the substrate, regulators inside the package, and power delivered from the back of the chip, which Intel introduced as PowerVia at Intel 18A and TSMC follows at A16.

The regulator suppliers are Vicor, Monolithic Power Systems, Infineon, Analog Devices, Texas Instruments and Renesas, with Silergy among the Chinese suppliers. Embedded passives come from Murata, TDK and Kyocera AVX. Device detail is on PMICs and VRMs.

Die-to-die links

Die-to-Die and Module Links

The link that couples dies and modules decides how many of them can work as one processor. Proprietary links lead in AI compute; open standards are catching up.

Die-to-die and module interconnects
LinkOwnerRole
NVLink and NVLink-C2CNVIDIAGPU-to-GPU and CPU-to-GPU links in every NVIDIA superchip; NVLink Fusion (2025) licenses it to other CPU and accelerator makers
Infinity FabricAMDChiplet fabric inside EPYC CPUs and Instinct accelerators
UCIeConsortium (Intel, AMD, Arm, TSMC, Samsung, Qualcomm, Google, Meta, Microsoft and others)Open die-to-die standard; version 3.0 (August 2025) doubled the data rate to 64 GT/s
UALinkConsortium (AMD, Intel, Google, Microsoft, Meta, AWS and others)Open scale-up link between accelerators; specification 1.0 released April 2025
CXLCXL ConsortiumCache-coherent link between CPUs, accelerators and pooled memory
BoW (Bunch of Wires)Open Compute ProjectSimpler, low-cost open die-to-die interface

China's chiplet effort runs on its own interface standards, because domestic designers cannot get leading-edge monolithic dies made and must combine several dies from older nodes instead; Huawei's Ascend 910C is the flagship example. Multi-die design is covered on Multi-Chip Modules.

Thermal design

Cooling Is Designed Into the Module

A package dissipating more than 1,000 W cannot be cooled by an air heatsink, so every current NVIDIA superchip and AMD MI355X module ships with a liquid cold plate. The thermal interface material between die and lid, the lid itself and the cold plate are module parts, chosen together with the package. The coolant loops, coolant distribution units and heat rejection that serve them are on DatacentersX.

Who integrates

Who Builds Modules

  • Compute modules: designed by NVIDIA, AMD, Google, AWS and Huawei; built by Foxconn, Quanta, Wistron and Wiwynn, mostly in Taiwan, Mexico and, since 2025, Texas.
  • Memory modules: HBM stacks are built by SK hynix, Samsung and Micron themselves; DIMMs and SSDs also by Kingston, ADATA and Longsys.
  • Power modules: built by the device makers, Infineon, STMicroelectronics, onsemi, Mitsubishi Electric, Fuji Electric and Rohm, with StarPower, BYD Semiconductor and CRRC rising in China.
  • RF and sensor modules: built by Skyworks, Qorvo, Broadcom, Qualcomm and Murata, and by camera module makers LG Innotek and Sunny Optical.

Record

Page Record

Covers
Module categories, flagship modules, power delivery, die-to-die links, thermal design and module integrators
Sources
NVIDIA, AMD, Huawei and Tesla product disclosures; UCIe and UALink consortia; TechCrunch (Dojo, August 2025); analyst reporting on Rubin power
Last verified
October 2026