Advanced Packaging Test

Advanced packaging test is the test discipline specific to multi-die modules — 2.5D AI accelerators, 3D stacked SoCs, HBM stacks, and the other module types that integrate multiple dies into a single package. Where Final Test in back-end assembly handles single-die packaged devices with a single post-package electrical test gate, advanced packaging modules require a test discipline spanning multiple gates through the assembly flow. The reason is structural: a multi-die module commits expensive silicon (logic dies, HBM stacks, advanced interposers) into a single assembly, and any defect in any component scraps the whole module. Test discipline is the economic discipline that makes advanced packaging viable at production yields.

Five test gates span a typical advanced packaging flow: wafer sort (die-level test before dicing, see Wafer Test (Sort)); known-good die (KGD) verification at singulated dies before assembly; interposer test before dies are loaded onto the interposer; in-process / mid-assembly test between integration steps; post-module electrical test on the finished module; and system-level test (SLT) running the module under application-representative workloads. Each gate exists because defects escaping one gate cost exponentially more to catch at subsequent gates — or escape to the customer.

The equipment base at the post-module electrical and SLT gates overlaps heavily with Final Test: Advantest and Teradyne ATE platforms, Cohu handlers, specialty test sockets and contactors. The distinctions from single-die Final Test come at the scale — test sockets for a thousands-of-signal AI accelerator module cost orders of magnitude more than a QFN test socket; thermal heads must dissipate hundreds of watts during test; ATE pin counts must scale into the tens of thousands. The fundamental ATE technology is shared; the test execution and infrastructure scales up dramatically for advanced modules.

The Known-Good Die Yield Problem

The structural reason advanced packaging test discipline is more intense than single-die test is yield compounding. If a multi-die module combines N dies, each tested at yield Y, the assembly yield from die-yield alone is Yⁿ — before any assembly defects. The math becomes punishing quickly.

The response is Known-Good Die (KGD) discipline — testing each die to high confidence before it enters the assembly flow. For modules with high die counts or expensive constituent components (leading-edge AI logic dies, HBM stacks), KGD is not optional. It adds a test step and adds cost, but prevents the geometric yield collapse that would otherwise occur.

KGD testing happens at two points: wafer-level test (the traditional wafer sort step, see Wafer Test (Sort)) screens dies while still on the wafer, and die-level test after singulation re-verifies each die before it commits to the module. Die-level KGD test is often at higher coverage than wafer sort — the wafer may have been sorted to 95% confidence for efficiency, but an expensive die committing to an AI accelerator module may be KGD-tested to 99.9%+ before placement. The economic calculation is simple: adding test cost is cheaper than scrapping an assembled module.

The Test Gate Sequence

A typical 2.5D AI accelerator module flows through multiple test gates. Each gate has a specific purpose; each has its own equipment and methodology.

Not every module flows through every gate. A simpler 2.5D module with lower component count may compress to wafer sort + post-module test + SLT. A complex 3D stacked module (HBM, SoIC with multiple tiles) typically flows through the full sequence. The test gate selection is a cost/yield engineering tradeoff made at the product level — for flagship AI accelerator modules at tens of thousands of dollars per unit, every test gate that might catch a defect is economically justified.

Interposer Test

Silicon interposers are fabricated objects with routing, TSVs, and copper layers that can be defective like any back-end-of-line product. An interposer test gate catches interposer defects before expensive dies are committed. Interposer testing uses either wafer-level probe cards (while the interposer is still part of an intact wafer) or post-singulation probe stations for individual interposers.

Test coverage at the interposer gate includes: short and open defects in the copper routing; TSV continuity; TSV resistance within spec; routing layer integrity; substrate contact pad integrity. Interposer test for large interposers (beyond-reticle, 3×-4× reticle area CoWoS modules) adds additional challenge because the probe card must contact thousands of test pads across a physically large area — specialty probe card design and test fixture thermal control become relevant at module scale.

Test fallout at the interposer gate is relatively small at mature fabrication yields (interposers are BEOL-quality products from foundry advanced packaging), but the economic justification is clear: a bad interposer that passes into assembly wastes the dies committed to it. For CoWoS-class modules, interposer test is routine at the foundry's advanced packaging line before die bonding.

Known-Good Stack (KGS) for HBM

HBM stacks are themselves multi-die assemblies (8, 12, or 16 DRAM dies plus a base die) produced at the HBM manufacturer's advanced packaging facilities. Before an HBM stack is shipped to a foundry for integration into a 2.5D AI accelerator module, it must be tested to known-good-stack (KGS) confidence. The KGS test is effectively the HBM equivalent of the multi-die module's post-module test, except it happens at the HBM producer (SK hynix, Samsung Memory, Micron) before the HBM stack leaves the memory vendor.

KGS test coverage includes full HBM protocol functionality, DRAM cell testing, thermal operation, and signal integrity across all stack pins. The discipline is mature — HBM vendors have been producing stacked-die memory products at production volume for over a decade, and KGS practice has evolved alongside HBM generations. SK hynix, Samsung, and Micron each have their own KGS infrastructure, with ATE platforms and test sockets specialized for stacked memory characterization.

When a KGS HBM stack arrives at a foundry for CoWoS, I-Cube, or similar 2.5D integration, it enters the flow already verified. The foundry's KGD testing of the accompanying logic die and the subsequent post-module test are what complete the module-level test coverage. KGS is upstream of the foundry's test discipline but it's the test gate that makes HBM-integrated 2.5D viable at production yields.

Post-Module Electrical Test

Post-module electrical test is the finished-module equivalent of Final Test for single-die packages. The module is inserted into a specialized test socket, the socket is mounted to a thermal head, the ATE fires test patterns, and the module's response is measured. For AI accelerator modules with thousands of signals, hundreds of watts of test-time power dissipation, and complex internal topology, the execution is significantly more demanding than single-die Final Test.

Test socket design for flagship AI accelerator modules has become a specialty engineering discipline in itself. The socket must contact thousands of pins or balls with repeatable low-resistance connections, dissipate multi-hundred-watt test-time power, and survive thousands of insertion cycles. Custom sockets for flagship modules are designed for specific package geometries and are qualified jointly by the package vendor, socket supplier, and test operator. Socket suppliers (Yamaichi, Ironwood, JF Technology) have developed specialty product lines for advanced-module test.

Active thermal control heads are required for high-power module test. A passive thermal head cannot absorb 500W during a 30-second functional test without the device self-heating to its thermal protection limits, which would cause the test to fail for thermal reasons rather than functional defects. Active cooling heads (circulating coolant or thermoelectric) keep the device in its target temperature window throughout the test cycle.

System-Level Test (SLT)

System-level test is the test methodology that runs a module in an application-representative fixture — essentially a motherboard-like test board with full software, drivers, and realistic workloads — rather than with synthetic ATE patterns. SLT exists because modern multi-die modules are complex enough that traditional ATE patterns cannot cover every failure mode. Some defects only manifest under specific software paths, cache coherency patterns, memory access patterns, or thermal conditions that synthetic patterns do not reproduce. SLT is the catch-all test for these "test escapes."

SLT has moved from specialty use into a mainstream final test gate for flagship modules over the last several years. The driving trend is complexity: a modern AI accelerator module has billions of transistors, thousands of memory cells, multiple HBM stacks, and complex multi-die interconnect that no synthetic pattern can fully exercise. SLT runs the actual workload the customer will run — AI training iterations, inference patterns, graphics rendering, memory stress tests — and catches failures that would otherwise escape to the customer.

SLT infrastructure is substantially more capital-intensive than ATE-based test. Each SLT slot requires:

SLT platforms come from Cohu (the handler market leader with SLT capability), Advantest, Teradyne (often with partner application boards), and specialty SLT integrators that build custom platforms for specific customers. NVIDIA, AMD, Intel, Apple, and hyperscaler custom-silicon customers operate substantial SLT capacity — often at the packaging line itself or at a dedicated test facility downstream — for flagship products.

Test time per module at SLT runs from minutes to hours depending on product and coverage target. This contrasts sharply with ATE-based test where throughput is measured in seconds per unit. The economic calculation favors SLT only when the product ASP justifies the slot cost and test time — flagship AI accelerators at tens of thousands of dollars each meet that bar; lower-ASP consumer parts typically do not. The adoption curve over the last several years has tracked the growing complexity of flagship modules and the rising cost of test escapes.

Test Escape Economics

The reason advanced packaging test discipline invests so heavily is test-escape economics at the module level. A test escape — a defective module that passes all electrical test gates and ships to the customer — fails at customer deployment. For a flagship AI accelerator in a hyperscaler datacenter, a failure may cost the customer hours of deployment troubleshooting, require board-level rework, trigger warranty replacement, or produce cascading failures in integrated systems. The cost per field-failure module for flagship AI silicon can run into tens of thousands of dollars in total remediation cost.

SLT and comprehensive post-module electrical test exist to drive the test-escape rate as low as possible. Target DPPM (defective parts per million) for flagship advanced modules runs below single-digit DPPM for high-quality lines — a bar achievable only through multi-gate test discipline including SLT. The test budget per module for flagship products can exceed 15% of total assembly cost, reflecting this discipline intensity. For comparison, single-die consumer MCU test budgets typically run at a few percent of device cost.

Equipment & Operators

Advanced packaging test capacity is concentrated at the foundries running the advanced packaging (TSMC, Samsung, Intel captive test), at the HBM producers for KGS (SK hynix, Samsung, Micron), at specialty test houses like KYEC (test-focused OSAT in Taiwan) that run dedicated test services for customers, and at major fabless customers' internal test infrastructure (NVIDIA, AMD, Apple, hyperscaler custom silicon programs all operate significant SLT capacity). The operator mix is more complex than traditional single-die Final Test because advanced modules touch multiple operators across their assembly and test flow.

Market Outlook

Advanced packaging test demand growth tracks AI accelerator, HPC, and flagship SoC volume — the same product categories driving advanced packaging demand. Specific growth drivers: SLT adoption expanding from flagship-only into mid-tier performance parts as complexity and test-escape costs rise; KGS test infrastructure expanding with HBM4 ramp; high-pin-count ATE investment expanding with module complexity; test socket specialty supply growth matching flagship package diversity.

The strategic equipment concentration pattern at the ATE layer (Advantest-Teradyne duopoly) and handler layer (Cohu leadership) remains stable. The SLT infrastructure supply is more distributed across ATE majors plus specialty integrators. Test capacity is generally tracking advanced packaging capacity growth, though SLT specifically has been a constrained capacity category at certain flagship programs — the combination of SLT per-slot cost and test time has required careful capacity planning at NVIDIA, AMD, and hyperscaler custom silicon programs.

Related Coverage

Parent: Advanced Packaging

Related test gates: Wafer Test (Sort) (upstream first-pass test) · Final Test (single-die post-package counterpart; shared ATE vendor base)

Architectures requiring this test discipline: CoWoS · Foveros · I-Cube · 3D IC (incl. SoIC) · SAINT

Upstream memory test context: HBM (KGS practice at HBM producers)

Cross-architecture reference: Comparison Matrix

Cross-pillar dependencies: AI Accelerators (primary SLT adoption driver) · Bottleneck Atlas