Adv Packaging
FO-WLP
l
Fan-Out Wafer-Level Packaging (FO-WLP) is an advanced packaging method that redistributes die I/Os over a larger area using redistribution layers (RDLs), without requiring a silicon interposer. FO-WLP allows ultra-thin packages, higher I/O density than traditional WLP, and cost-effective multi-die integration. It is widely adopted in mobile, IoT, automotive, and consumer devices, and serves as the foundation for several proprietary platforms (e.g., TSMC InFO, ASE FOCoS, Amkor SWIFT).
Process Overview
- Step 1: Dies are placed face-down in an epoxy mold compound to form a reconstituted wafer.
- Step 2: Redistribution layers (RDLs) are built on top of the mold, rerouting I/O pads to a larger pitch.
- Step 3: Additional dies or passives can be added side-by-side for SiP configurations.
- Step 4: Solder balls or copper pillars are added for board-level connections.
- Step 5: The package is singulated and tested before shipping.
Key Features
- Ultra-Thin: Eliminates the need for substrates and interposers, enabling thin profiles for mobile devices.
- High-Density I/O: RDL enables finer pitches than conventional WLP, supporting larger dies and multi-die layouts.
- Scalable Integration: Can support heterogeneous SiPs (logic, memory, RF, passives).
- Cost Efficiency: More cost-effective than silicon interposer-based packaging (e.g., CoWoS).
Applications
- Mobile SoCs: Smartphones and tablets, particularly RF and application processors.
- Automotive: Advanced driver-assistance systems (ADAS), radar, infotainment chips.
- IoT Devices: Low-power, small-footprint packages for edge devices and sensors.
- Consumer Electronics: Wearables, audio processors, RF front-end modules.
Representative Platforms & Providers
Platform | Provider | Specialty | Example Applications |
---|---|---|---|
InFO (Integrated Fan-Out) | TSMC | High-performance mobile packaging, SiP variants | Apple A-series, M-series SoCs |
FOCoS (Fan-Out Chip-on-Substrate) | ASE | High-density FO-WLP integrated with organic substrates | Networking, HPC ASICs |
SWIFT & SLIM | Amkor | High-performance fan-out with fine-pitch RDL | AI, automotive, networking |
Advantages & Constraints
- Advantages: Thin form factor; cost-effective vs 2.5D interposers; scalable for multi-die SiPs; widely adopted in consumer and automotive.
- Constraints: Warpage issues in large reconstituted wafers; limited for extreme bandwidth applications (AI/HPC); process yield challenges in very fine-pitch RDLs.
Cleanroom & Environment
- Performed in Class 1000–10,000 packaging lines.
- Mold reconstitution requires precision die placement and void-free encapsulation.
- Reliability challenges include warpage, moisture sensitivity, and thermal cycling stress.
Market Outlook
Fan-Out WLP has become the dominant packaging solution for mobile and consumer devices, with TSMC InFO leading in high-performance SoCs and OSATs driving broader adoption across IoT and automotive. Through 2030, FO-WLP will remain critical for cost-sensitive applications, while interposer-based (CoWoS, I-Cube) and 3D (Foveros, hybrid bonding) dominate AI/HPC. FO-WLP capacity expansion is expected to align with growing demand for SiPs in automotive and IoT markets.