CoWoS: TSMC Chip-on-Wafer-on-Substrate

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's 2.5D advanced packaging architecture and the most strategically important packaging technology in the semiconductor industry. Every NVIDIA H100, H200, B100, B200, GB200 and Rubin generation GPU and every AMD MI300 and MI400 series AI accelerator ships on CoWoS, and the major hyperscaler custom AI chips (Google TPU, Amazon Trainium and Inferentia, Microsoft Maia) depend on CoWoS capacity allocation. The Tesla AI5 chip is among the incoming CoWoS customers at TSMC Arizona. CoWoS capacity is the main global supply constraint on AI accelerators: TSMC has roughly doubled it each year since 2023, and demand has still outrun supply.

All three CoWoS variants place a logic die and several high-bandwidth memory (HBM) stacks side by side on a carrier that routes the signals between them. CoWoS-S uses a full silicon interposer, CoWoS-R a redistribution layer (RDL) interposer and CoWoS-L local silicon bridges in an organic carrier. TSMC makes the carriers and assembles the modules in its own captive lines; there is no merchant market for CoWoS interposers or CoWoS-assembled modules.

CoWoS Package Structure

The name describes the three layers of the finished module: chips (a logic die and two or more HBM stacks) on a wafer (the silicon interposer, made with through-silicon vias (TSVs) and back-end-of-line (BEOL) routing at TSMC) on a substrate (an organic flip-chip ball grid array (FCBGA) laminate built with Ajinomoto Build-up Film (ABF) that connects to the board).

Layer	Role	Fabrication
Chip (top)	Logic die plus multiple HBM stacks placed side by side; interconnected through the interposer below	Logic die at TSMC leading-edge process; HBM stacks at SK hynix, Samsung, or Micron (external)
Wafer (middle, interposer)	Silicon, RDL, or silicon-bridge carrier providing fine-pitch routing between chips and a vertical path to the substrate below	Fabricated at TSMC advanced packaging facilities using BEOL copper damascene processes
Substrate (bottom)	Organic FCBGA carrier providing the BGA ball interface to the board; coarser routing for power, ground, lower-speed I/O	ABF-based FCBGA from Unimicron, Ibiden, Nan Ya PCB, Shinko, or AT&S (external)

Assembly starts with "chip on wafer": the logic die and HBM stacks are bonded to the interposer while it is still part of an intact wafer. The populated interposer wafer is then thinned, diced and mounted on the organic substrate, and underfill, encapsulation and lid attach complete the module. Assembly runs at TSMC advanced packaging sites in Taiwan, with more capacity ramping at TSMC Arizona.

CoWoS-S, CoWoS-R and CoWoS-L

The three variants sit at different points on a cost and performance curve. TSMC assigns each customer the variant that fits its bandwidth requirement, interposer area and cost target.

Variant	Carrier	Position
CoWoS-S	Full silicon interposer with TSVs and BEOL copper routing; covers full module footprint	Highest bandwidth, highest cost, highest capacity pressure; the flagship AI accelerator carrier
CoWoS-R	RDL interposer on organic substrate; copper routing in thin-film polymer stack	Lower bandwidth and cost than CoWoS-S; for customers that do not need maximum silicon-interposer density
CoWoS-L	Local silicon interconnect bridges embedded in organic carrier; bridges handle die-to-die routing, organic handles the rest	Bridge-based cost optimization; between CoWoS-R and CoWoS-S; similar in concept to Intel EMIB

CoWoS-S is the incumbent volume variant, and industry references to "CoWoS capacity" usually mean CoWoS-S. CoWoS-L is growing among customers that need CoWoS-level integration without the cost of a full silicon interposer, which also eases pressure on CoWoS-S capacity. CoWoS-R serves mid-performance customers and specialty applications.

Early CoWoS-S interposers fit within one lithography reticle field, about 858 mm² at TSMC's reticle limit. Current AI accelerator modules use stitched interposers three to four times that size or larger, and TSMC has extended this capability with each generation. No alternative architecture yet matches CoWoS-S on beyond-reticle interposer size.

HBM Integration on CoWoS

CoWoS exists mainly to connect HBM stacks to logic dies at a bandwidth no organic substrate can carry. A current AI accelerator package holds a logic die surrounded by two, four, six, eight, 12 or more HBM stacks. Each stack has more than 1,000 signal pins to the logic die, so a full module carries tens of thousands of die-to-HBM connections.

The interposer carries those signals at the required pitch and density. BEOL routing on its top surface handles horizontal die-to-die traffic, and its TSVs carry vertical paths down to the substrate. TSV and micro-bump detail is on Advanced Interconnects, and the memory side on HBM.

CoWoS has advanced in step with HBM2, HBM2E, HBM3, HBM3E and HBM4. HBM4 uses hybrid bonding between the DRAM dies inside the stack, which improves stack height and heat flow, but the stack still joins the CoWoS interposer through micro-bumps at 40 to 55 µm pitch. Hybrid bonding at the interposer interface is expected later this decade.

CoWoS Customers

Every major AI accelerator program in volume production either uses CoWoS or has announced a roadmap on it.

Customer	Products on CoWoS	Notes
NVIDIA	H100, H200, B100, B200, GB200, GB300, Rubin generation	Largest single CoWoS customer by volume; capacity allocation is a quarterly strategic concern for both companies
AMD	Instinct MI300 series, MI400 series	Primary AI accelerator line on CoWoS; volume growing alongside NVIDIA
Google	TPU v4, v5, v5p, v6 family	Hyperscaler custom AI silicon; long-standing CoWoS customer
Amazon	Trainium, Inferentia series	AWS custom AI silicon; growing CoWoS capacity allocation
Microsoft	Maia AI accelerator	Hyperscaler custom AI silicon in production
Tesla	AI5 at TSMC Arizona (captive allocation)	Captive TSMC Arizona CoWoS capacity; feeds Tesla's in-house AI5 program ahead of the Terafab AI6 transition
Broadcom	Hyperscaler custom-silicon partner products; networking AI application-specific integrated circuits (ASICs)	Significant CoWoS consumer through custom silicon business
Marvell	Hyperscaler custom AI silicon partner products	Growing CoWoS consumer through custom silicon partnerships

CoWoS Capacity

CoWoS capacity has been the most closely watched figure in semiconductor manufacturing since the AI buildout accelerated in 2023. TSMC reports CoWoS expansion every earnings cycle, fabless AI accelerator companies cite CoWoS allocation as a driver of their shipment ramps, and hyperscalers track CoWoS output. Supply stays tight because:

CoWoS is a near-sole-source technology at TSMC
interposer fabrication is capital-intensive and has long cycle times
demand has outgrown every capacity expansion so far

TSMC has guided continued aggressive expansion through the rest of the decade, in Taiwan and in Arizona as part of its CHIPS Act-era buildout. Samsung Foundry's I-Cube is the closest competing architecture but runs at much smaller scale with fewer customers, Intel EMIB (Embedded Multi-die Interconnect Bridge) serves a different segment, and no merchant outsourced semiconductor assembly and test (OSAT) provider runs equivalent capacity. 3D hybrid bonding through TSMC SoIC (System on Integrated Chips) and Intel Foveros Direct will take over some die-on-die integration from CoWoS as chiplet designs mature. See 3D IC Packaging.

CoWoS Supply Chain Inputs

Input	Source	Concentration
Logic die	TSMC leading-edge process (N5, N4, N3, N2 as generations advance)	Sole source at TSMC for most leading-edge AI accelerator silicon
HBM stacks	SK hynix (dominant), Samsung, Micron	SK hynix leadership through HBM3/HBM3E; Samsung and Micron competing at HBM4; see HBM
Silicon interposer fabrication	TSMC captive advanced packaging facilities	TSMC-exclusive; no merchant capacity at CoWoS-equivalent density
FCBGA organic substrate	Unimicron, Ibiden, Nan Ya PCB, Shinko Electric, AT&S	Five-supplier oligopoly; ABF laminate single-sourced at Ajinomoto; see Substrates & Interposers
Flip-chip and micro-bump bonding	BESI, ASMPT, Kulicke & Soffa (thermocompression bonders)	High-accuracy tool supply concentrated at BESI and peers; see Flip-Chip Bonding
Advanced packaging test	Advantest, Teradyne, specialty system-level test (SLT); TSMC captive module test	See Advanced Packaging Test

CoWoS Production Locations

CoWoS production is concentrated at TSMC advanced packaging facilities in Taiwan. TSMC's Arizona advanced packaging capacity, ramping under CHIPS Act support, serves the logic dies from TSMC Arizona fabs and is allocated to specific customer programs, Tesla AI5 among them, instead of the broad CoWoS customer base. Japan supplies substrates and materials but does not host CoWoS assembly.

The Taiwan concentration has driven industrial policy responses in the CHIPS Act and in European, Japanese and Korean programs, which treat CoWoS, leading-edge fabrication and HBM production as national security bottlenecks because every AI accelerator depends on them. CoWoS and equivalent capacity is expected to spread geographically over the next decade, with Taiwan remaining the center.

CoWoS Market Outlook

CoWoS demand is expected to grow faster than any other advanced packaging category through the end of the decade, driven by:

AI accelerator production: continued ramp of GPU and accelerator output.
HBM count per module: each new accelerator generation carries more HBM stacks, which needs larger interposers and more CoWoS area per unit.
Hyperscaler custom silicon: expanding programs at Google, Amazon, Microsoft and their design partners.
New entrants: custom-silicon programs at more hyperscalers, enterprise AI accelerators and specialty AI silicon.

TSMC's capacity plans have consistently fallen short of demand, and CoWoS is expected to remain a constraint through the decade. Samsung I-Cube and Intel EMIB serve different segments and are not volume substitutes at the flagship AI accelerator tier. Over the longer term, 3D hybrid bonding (TSMC SoIC, Intel Foveros Direct and next-generation Samsung SAINT) will take over some functions, particularly die-on-die logic stacking, while HBM-plus-logic 2.5D integration stays with CoWoS. Larger beyond-reticle interposers and hybrid bonding at the HBM-to-interposer interface are the next technical steps.

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CoWoS Packaging