Silicon Photonics Fabs

Silicon photonics fabrication is the forward-looking archetype in the twelve-way fab taxonomy — smaller in current volume than established archetypes like DRAM or leading-edge logic but strategically critical to the next wave of datacenter compute infrastructure. Silicon photonics integrates optical waveguides, modulators, photodetectors, and passive optical components into CMOS-compatible silicon processes, creating chip-scale optical circuits that can be manufactured at semiconductor fab volumes and economics. The central strategic driver is AI training cluster interconnect scaling: as AI accelerator clusters grow beyond single-rack configurations, electrical copper interconnect faces fundamental signal integrity limits at 800Gbps+ speeds over distances beyond approximately 10–20 meters. Optical interconnect — silicon photonics-based transceivers, and emerging co-packaged optics (CPO) where optical I/O integrates directly into accelerator and switch packages — is the scaling path beyond electrical limits. Every large AI training cluster in production today uses optical interconnect; every future AI cluster at scale will use more of it.

The archetype has a structural characteristic that shapes everything about its supply chain: silicon cannot efficiently generate light. Silicon is an indirect bandgap semiconductor, so it does not emit photons efficiently when carriers recombine. Every silicon photonics design therefore requires external III-V semiconductor laser sources (typically InP-based) integrated with the silicon photonic circuit. This integration creates a structural dependency between silicon photonics fabs and III-V compound semiconductor fabs (covered at III-V Compound Semiconductor) — the two archetypes cannot produce viable silicon photonics products independently. This is a structural cross-archetype dependency that most other archetypes do not have.

The Post-Electrical Interconnect Thesis

The strategic case for silicon photonics rests on concrete physics limits of electrical interconnect. Copper PCB traces and electrical cables face signal attenuation that scales with frequency and distance — a signal at 112 Gbps requires active signal conditioning beyond approximately 1 meter in practical PCB designs, and beyond approximately 10–20 meters in high-performance cable assemblies. As data rates scale to 224 Gbps and beyond at each lane, and as aggregate bandwidths scale to 1.6 Tbps and 3.2 Tbps per port, these distance limits tighten further. At some point electrical interconnect reaches a wall where either the data rate or the distance must be reduced.

Optical interconnect has no equivalent distance-attenuation wall at these data rates. A single-mode fiber carrying 1.6 Tbps signals loses a few tenths of a dB per kilometer — negligible compared to the tens of dB per meter of electrical interconnect at the same data rate. Optical links can run from rack to rack across a datacenter, or from datacenter to datacenter across campus, with no need for signal regeneration. The economic question historically has been whether the cost of electrical-to-optical and optical-to-electrical conversion at each end justifies the improved distance characteristic. For short interconnects (intra-board, close-range backplane) electrical has been cheaper. For longer interconnects (rack-to-rack, datacenter-to-datacenter) optical has been essential.

The shift happening now is that the break-even distance is dropping. Improvements in silicon photonics integration and cost reduction are pushing optical economics toward shorter distances, while electrical interconnect performance at ultra-high data rates is becoming structurally limited. AI training clusters — with their extreme bandwidth requirements across large physical extents — have become the application that drives the economic shift toward shorter-distance optical interconnect including co-packaged optics. What was once exclusively a telecom and datacenter networking technology is becoming an accelerator and compute-adjacent technology.

Three Main Product Categories

Silicon photonics production today serves three distinct product categories with different technology maturity levels and growth trajectories.

Pluggable optical transceivers are the volume backbone today — hyperscale datacenter buildouts deploy millions of 400G and 800G transceivers annually, with 1.6T ramping. Silicon photonics has captured increasing share of this market as data rates have scaled, because silicon photonics processes can integrate modulators, multiplexers, and detectors at densities that discrete III-V components cannot match at comparable cost. Co-packaged optics is the emerging strategic category — reducing the electrical distance between ASIC and optical I/O from centimeters (pluggable) to millimeters (CPO) enables higher total bandwidth per package and reduces the electrical driver power required. Coherent optics for telecom is a mature specialty segment where silicon photonics has displaced some traditional InP-dominant production at cost-sensitive tiers.

Co-Packaged Optics — The Strategic Inflection

Co-packaged optics (CPO) is the technology transition that determines silicon photonics' strategic importance over the next half-decade. In a pluggable transceiver architecture, the electrical signal travels from the switch or accelerator ASIC across the PCB, through a connector, and into a pluggable transceiver module that sits at the edge of the switch chassis (typically 10–30 cm from the ASIC). The electrical-to-optical conversion happens inside the transceiver. At data rates approaching 224 Gbps per lane, this electrical distance becomes increasingly difficult to drive cleanly.

In a co-packaged optics architecture, the optical I/O is integrated into the same package as the switch ASIC or accelerator ASIC — typically as photonic chiplets sitting adjacent to or stacked with the primary compute/switch die. The electrical signal path from ASIC to optical conversion shrinks from centimeters to millimeters, dramatically reducing the signal-integrity challenge. The tradeoff is packaging complexity — optical chiplets are more thermally sensitive than logic chiplets, and optical connections to external fibers require specialty interposers and fiber-coupling structures. CPO is significantly harder to manufacture and assemble than pluggable transceivers, but the electrical and thermal advantages at ultra-high data rates are substantial.

The operator landscape for CPO is forming across multiple paths. Broadcom Bailly is a first-generation CPO platform for datacenter switches, integrating optical I/O with switch ASIC silicon. NVIDIA co-packaged optics programs are under development for AI accelerator integration at future GPU generations. Intel Ayar Labs provides optical I/O chiplet technology ("TeraPHY") that couples to various customer ASIC platforms. Lightmatter Passage is a specialty photonic interposer technology targeting multi-chiplet AI accelerator architectures. TSMC COUPE is an emerging silicon photonics foundry platform structured around 3D integration with TSMC advanced logic for exactly this CPO-era use case.

The CPO transition has similar strategic structure to the CoWoS transition a decade ago — a new packaging technology that binds together multiple die types (logic + optical in CPO's case; logic + memory in CoWoS's case) in ways that create a new production bottleneck that gates end-product shipment. Whether CPO capacity at TSMC, Broadcom, Intel, or emerging operators scales fast enough to meet AI accelerator demand will be one of the defining supply chain questions of 2026–2030.

The Silicon + III-V Integration Requirement

Silicon's indirect bandgap makes it a fundamentally poor material for generating light efficiently. In indirect bandgap semiconductors, electron-hole recombination mostly dissipates energy as heat rather than as photons. This physical reality means silicon photonics cannot include silicon-based lasers — every silicon photonic circuit requires an external III-V laser source integrated via one of several approaches.

Hybrid integration places a separately-fabricated InP laser die adjacent to the silicon photonic die, with optical coupling between the two via facet polishing, grating couplers, or other techniques. Simple and mature but requires careful alignment and adds packaging complexity. Heterogeneous integration bonds InP material (a few micrometers of InP epi layer) directly onto the silicon photonic wafer, enabling the laser structure to be fabricated by subsequent processing on the bonded InP layer. More complex process but results in tighter integration. Flip-chip bonding of pre-fabricated InP laser dies onto silicon photonic wafers at specific locations. Used at volume for some applications. Monolithic integration — growing InP epi layer directly on silicon via specialty epitaxy — has been pursued for decades as a research target but has not reached commercial volume at high performance.

The dependency on III-V laser sources ties silicon photonics' supply chain to the III-V substrate and epi supply chains covered at III-V Compound Semiconductor. Silicon photonics scale-up beyond certain volumes would stress InP substrate supply at the same operators (Sumitomo, JX Nippon, AXT, Wafer Technology) that serve telecom optics and LiDAR detection. This is the specific cross-archetype dependency that silicon photonics industry planners must account for — you cannot scale silicon photonics production without simultaneously scaling InP substrate supply, and InP substrates come from a narrow global supplier base.

Operator Landscape

The Foundry Platform Competition

Silicon photonics foundry access is a critical competitive variable because many silicon photonics operators are fabless (Broadcom, Ayar Labs, Lightmatter, specialty startups) and depend on merchant foundry capacity to produce their designs. The foundry platform competition has three significant players at 300mm scale plus specialty operators at 200mm.

GlobalFoundries Fotonix has been the leading merchant silicon photonics foundry for several years, with 300mm capacity at Malta NY, broad customer base across datacenter, telecom, and specialty applications, and multiple process design kits (PDKs) optimized for different application targets. GF's Fotonix platform supports pluggable transceivers, emerging CPO applications, and specialty silicon photonics designs. The 300mm scale and broad customer access make GF Fotonix the reference merchant silicon photonics platform globally.

TSMC COUPE is emerging as a strategic silicon photonics foundry option structured around integration with TSMC's advanced logic capability. The distinction is that COUPE is positioned specifically for CPO-era applications — silicon photonic chiplets designed for 3D integration with TSMC N3 or N2 logic dies in the same package. Whether COUPE scales to merchant silicon photonics foundry capability matching GlobalFoundries Fotonix, or remains primarily a specialty platform for TSMC logic customers, is an open competitive question. TSMC has specific competitive advantages — deep relationships with AI accelerator customers, integrated advanced packaging capability (CoWoS, SoIC, emerging CPO-adjacent technologies), and scale that specialty silicon photonics operators cannot match.

Intel Foundry (post-Tower acquisition) inherits specialty silicon photonics capability from Tower Semiconductor and Intel's internal photonics program. Intel's silicon photonics position is complex — Intel has both captive silicon photonics for internal products and foundry capacity serving external customers through Intel Foundry Services. How these integrate operationally is a 2024–2026 strategic question.

IMEC serves a different role as a research consortium with pilot-line production capability. IMEC is where much silicon photonics process development has happened, and IMEC pilot-line capacity enables early customer engagements before committing to volume merchant foundry production. IMEC is not a volume supplier but its role in the industry R&D chain is substantial.

Cross-Network: The Primary SX-DX Interface

Silicon photonics is the primary SX-DX interface archetype — the technology where semiconductor manufacturing most directly enables the scaling of AI datacenter compute infrastructure. Every large AI training cluster deployed today uses optical interconnect at some tier of the network architecture (intra-rack high-bandwidth interconnect may use electrical, but rack-to-rack and larger scales use optical). As AI training clusters scale from single-rack through multi-rack through datacenter-scale deployments, the share of interconnect that must be optical grows, and the economic value of improved optical interconnect performance grows with it.

The specific SX-DX connections include: pluggable transceiver demand scaling with AI cluster buildout (hundreds of thousands to millions of transceivers per AI training cluster at scale); co-packaged optics transition as AI accelerator architectures move toward CPO integration; coherent optics for datacenter-to-datacenter AI training synchronization; and photonic interposer technology for multi-chiplet AI accelerator architectures. Each of these connections represents silicon photonics capacity that must be available when AI infrastructure demand requires it.

Beyond AI, silicon photonics has secondary cross-network connections. Automotive LiDAR uses silicon photonics + InP laser combinations for FMCW LiDAR architectures — the SX-EX interface via autonomous vehicle sensing (see III-V Compound Semiconductor for the related InP-based LiDAR semiconductor coverage). Telecom access networks at PON (passive optical network) and metro scales use silicon photonics at cost-optimized tiers. Quantum computing uses silicon photonics for specific photonic qubit platforms (PsiQuantum specifically). But the AI cluster interconnect story is structurally the largest and the most strategically significant.

The Consolidation Dynamic

Silicon photonics has been characterized by continuous industry consolidation over the past decade. Cisco acquired Acacia Communications in 2021 for coherent optics silicon photonics capability. Lumentum acquired Cloudlight for datacom silicon photonics. II-VI and Coherent merged in 2022, consolidating photonic component capability including silicon photonics. Intel acquired Tower Semiconductor in 2024, inheriting specialty silicon photonics foundry capability. Additional tuck-in acquisitions and consolidations are common.

The consolidation dynamic reflects silicon photonics' strategic importance as a capability — operators in networking, AI compute, and advanced packaging increasingly treat silicon photonics as a capability they must either build or buy. For operators like Cisco, Broadcom, and hyperscalers, acquiring or internalizing silicon photonics capability removes strategic dependency on merchant suppliers for a technology critical to their core products. For pure-play silicon photonics operators, scale advantages at larger organizations can accelerate product development and market access. The net trend is fewer independent silicon photonics operators over time and more consolidation into larger integrated companies.

Fabs in This Archetype

Notable silicon photonics fabs and operations include: GlobalFoundries Fab 8 Malta NY (Fotonix 300mm primary); GlobalFoundries Fab 9 Burlington VT (specialty silicon photonics); TSMC Taiwan operations (COUPE emerging alongside advanced logic); Intel Hillsboro OR (silicon photonics integrated with Intel fabs); Intel Foundry Migdal Haemek Israel (Tower heritage silicon photonics); IMEC Leuven Belgium (pilot line); Cisco/Acacia captive operations; Lumentum silicon photonics operations; Coherent post-merger sites; Broadcom fabless silicon photonics production; Ayar Labs fabless operations using Intel capacity; Lightmatter fabless operations; specialty silicon photonics operators at various scales. See Fab Facilities for the full inventory.

Related Coverage

Parent: Wafer Fabs

Peer archetype pages: Leading-Edge Logic · Mature Logic · DRAM · 3D NAND · SiC Power · GaN Power & RF · Analog & Mixed-Signal · CMOS Image Sensor · MEMS · III-V Compound Semiconductor · Rad-Hard & Rad-Tolerant

Critical cross-archetype dependency: III-V Compound Semiconductor (InP laser sources for silicon photonics)

Advanced packaging connection: Foundry Captive Packaging · 3D IC · Advanced Interconnects (emerging CPO integration with advanced packaging)

Cross-pillar dependencies: Optical Transceivers · Co-Packaged Optics · AI Accelerators (CPO integration customers)

Cross-network AI infrastructure: AI Cluster Interconnect (emerging DX page) · Datacenter Networking (emerging DX page)