DRAM Fabs

DRAM fabrication

How a DRAM Fab Differs From a Logic Fab

A DRAM cell stores one bit as charge in one capacitor, switched by one transistor (1T1C). Packing billions of these cells onto a die takes two structures logic fabs do not build.

• Buried wordline (BWL) transistor: the gate is recessed into a trench in the silicon, instead of sitting above it as in planar or FinFET logic, to fit the most cells into the smallest area. It takes precision etch and fill of deep trenches.
• Capacitor-over-bitline (COB): the storage capacitor is a tall cylinder built above the bitline wiring, with aspect ratios above 50:1 at leading nodes. It takes high-aspect-ratio etch and specialty dielectric deposition.

The periphery around the cell array, address decoders, sense amplifiers, I/O and control logic, uses logic-like processes on the same wafer, so a DRAM wafer carries two process zones. Logic makers seldom enter DRAM production and DRAM makers seldom enter leading-edge logic, even though both buy from the same equipment categories. DRAM chip types and markets are on DRAM Memory Chips.

Node generations

DRAM Node Names and Generations

DRAM nodes use generation names that differ from logic node names, and the same name does not mean exactly the same capability at each maker.

DRAM scaling has slowed. Each generation adds about 15% to 25% bit density, against the doubling per generation of the 2000s. The capacitor must hold enough charge to resist leakage, which limits how small it can get, so density now comes from taller capacitors and new dielectrics as much as from transistor shrink.

EUV in DRAM

EUV Lithography in DRAM

Samsung was the first DRAM maker to use extreme ultraviolet (EUV) lithography in volume, at D1z in 2020. SK hynix followed at comparable generations. Micron ran 1-alpha and 1-beta on deep ultraviolet (DUV) multi-patterning and introduced EUV at 1-gamma. CXMT has no disclosed production EUV use, and US and Dutch export controls block it from buying EUV scanners.

DRAM uses EUV on far fewer layers than logic, typically two to five per wafer against 20 or more at advanced logic: the tightest-pitch patterns in the cell array and select periphery wiring. ASML scanners are covered on ASML EUV Scanner.

HBM and capacity

HBM Pulls Wafers From Commodity DRAM

HBM stacks 8, 12 or 16 DRAM dies on a base logic die, connected by through-silicon vias. It is built from the same wafers as DDR5, so every wafer moved to HBM is one less for commodity DRAM.

• Share: SK hynix supplied 50% of HBM in the second quarter of 2026, Samsung 33% and Micron 18%, per Counterpoint. For full-year 2025, SK hynix held about 63%.
• HBM4 for NVIDIA Rubin: all three makers are shipping or in volume production. Reports differ on who holds the largest share of Rubin orders.
• Base die: SK hynix buys its HBM4 base die from TSMC on a 12nm-class process. Samsung makes its own on its 4nm foundry process. Micron makes its HBM4 base die in-house and moves HBM4E to TSMC.

HBM generations, stack construction and supplier positions are on High Bandwidth Memory.

Makers

DRAM Makers

DRAM fabs

DRAM Fabs and US Production Status

Each row is a DRAM fab or HBM plant from the SemiconductorX fab dataset, banded by whether it produces in the United States.

• Some US volume
• US planned
• Made abroad

Production by country

Where DRAM Is Made

• South Korea: Samsung Pyeongtaek and Hwaseong, and SK hynix Icheon and Cheongju. On the capacity estimates above, Korea holds more than half of world DRAM wafers and nearly all HBM.
• China: CXMT Hefei and SK hynix Wuxi. CXMT's estimates range from about 320,000 to 350,000 wafers a month, rising toward 420,000 by 2027.
• Taiwan: Micron Taichung, Micron's largest DRAM site, plus Nanya and Winbond.
• Japan: Micron Hiroshima.
• United States: Micron Manassas has made 1-alpha DRAM since May 2026, for long-life DDR4 and LPDDR4 parts. Micron Boise ID1 starts wafers in mid-2027 and ID2 in late 2028; Clay, New York follows around 2030. SK hynix's West Lafayette, Indiana plant will package HBM from the second half of 2029.

CXMT

CXMT: Commodity Scale, HBM Next

CXMT moved from DDR4 in 2019 to DDR5 and LPDDR5, which now make up about three-quarters of its output. It sells to Chinese phone makers, Chinese servers and consumer electronics, with growing exports, and it raised about $8.6 billion in a STAR Market listing in July 2026.

• Leading-edge DRAM: CXMT production sits generations behind 1-beta and 1-gamma at the three leaders. Catching up needs EUV, which export controls withhold.
• HBM: CXMT is sampling 8-high HBM3 to Huawei, with reported yields around 25% and mass production targeted for the end of 2026.
• US designations: CXMT is on the Pentagon's 1260H list of Chinese military companies, having been removed in February 2026 and added back in June; it sued the Pentagon in August 2026. It is not on the Commerce Department's Entity List.

China's wider position is on the China Bifurcation spotlight.

Market cycles

DRAM Market Cycles and Capacity Decisions

DRAM has been the most cyclical segment in semiconductors. A memory fab takes two to three years to build and one to two years to ramp, so capacity ordered in a boom often arrives in the next downturn. The 2022 to 2023 downturn brought heavy losses; recovery began in 2024 on HBM demand, and DRAM revenue rose about 60% from the first to the second quarter of 2026 as supply fell behind demand.

HBM demand follows AI accelerator output and hyperscaler spending, which run on different cycles from PC and phone demand. HBM prices are higher and steadier than commodity prices, so the three leaders are partly insulated from the commodity cycle, while CXMT's added commodity output pushes those prices down.

Related coverage

Related Coverage

• High Bandwidth Memory
• DRAM Memory Chips
• 3D NAND Fabs
• Leading-Edge Logic Fabs
• Samsung Semiconductor
• US Reshoring
• Rack supplier rings on DatacentersX