Wafer Fabs Overview

A wafer fab is the physical facility where raw semiconductor substrates are transformed into patterned wafers carrying functioning transistors. This is the front-end of semiconductor manufacturing — the step that produces the circuit patterns on silicon (or SiC, GaN, InP, GaAs) before the wafer is diced, packaged, and tested. Every chip on every page of this network passes through a wafer fab. The global inventory of wafer fabs numbers in the hundreds — but the variety among them is extreme. Twelve distinct fab archetypes serve structurally different purposes, operate with different tool configurations, consume different chemistries, and compete in different markets. A SiC power device fab and a leading-edge logic fab share vocabulary but almost nothing else.

This hub page catalogs the 12 wafer fab archetypes that define the global manufacturing landscape. Each archetype has its own dedicated page (planned) that goes deep on operator dynamics, geographic distribution, process specifics, and strategic character. The inventory of individual fabs is available via the Fab Facilities dataset and will be split into filtered views per archetype on the grandchild pages.

The Twelve Fab Archetypes

Semiconductor fabs partition into distinct archetypes that share vocabulary but operate as fundamentally different industrial systems. A SiC boule-growth-and-device facility cannot produce a leading-edge logic chip regardless of capital invested — the substrate physics, tool configuration, and process chemistries are incompatible. Understanding which archetype a given fab belongs to is prerequisite to understanding what it produces, who competes with it, and what supply chain it serves.

Why the Archetypes Don't Substitute for Each Other

The central observation about the twelve archetypes is that they are not substitutable — a SiC power fab cannot be reconfigured to produce leading-edge logic without effectively rebuilding the facility. The incompatibilities compound across multiple layers. The substrate itself differs (silicon vs. SiC vs. GaN-on-Si vs. GaN-on-SiC vs. InP vs. GaAs). The tool configuration differs (leading-edge logic requires EUV scanners that no other archetype uses; SiC requires high-temperature anneal furnaces that no silicon fab uses; MEMS requires suspended-structure release that no other archetype uses). The process chemistries differ (photoresists, etch gases, precursors, slurries — all optimized per substrate and process type). The qualification regimes differ (AEC-Q100 automotive vs. QML-V space vs. standard commercial). The customer relationships differ (foundry-fabless for logic; IDM for memory; specialty captive for rad-hard). Each archetype is effectively a separate industry that shares only the word "semiconductor" with the others.

The practical consequence is that supply chain risk analysis must be archetype-specific. A TSMC Hsinchu disruption affects leading-edge logic globally — it does not affect SiC power device supply, MEMS supply, or rad-hard processor supply, which are produced at entirely different fabs by entirely different operators. Conversely, a Wolfspeed restructuring event affects global SiC supply — it does not affect leading-edge logic. Aggregated "semiconductor supply chain" risk frameworks that treat the industry as a single entity obscure the archetype-specific concentrations that actually determine where disruptions bite.

Geographic Concentration Summary

Each archetype has its own geographic concentration pattern. Leading-edge logic concentrates in Taiwan (~90% of sub-5nm production at TSMC). Memory concentrates in South Korea (~70% of global memory at Samsung and SK hynix). 3D NAND adds Japan-centered capacity (Kioxia, Western Digital partnership). SiC concentrates in the US (Wolfspeed), Europe (STMicro, Infineon, Bosch), and Japan (Rohm, Mitsubishi), with China scaling via SICC. CIS concentrates in Japan (Sony). MEMS distributes across Europe (Bosch, STMicro), US (ADI, NXP, TDK-InvenSense), and Japan. Rad-hard concentrates in the US (BAE, Honeywell, Microchip, TI QML, SkyWater, GlobalFoundries) due to DMEA accreditation requirements that cannot be replicated abroad.

The CHIPS Act and EU Chips Act are reshoring programs focused primarily on leading-edge logic (TSMC Arizona, Samsung Taylor, Intel Ohio/Arizona, Rapidus Hokkaido, Intel Magdeburg) and DRAM (Micron Clay NY/Boise, Samsung Pyeongtaek expansion). The programs are less focused on mature logic, SiC, GaN, MEMS, CIS, and rad-hard — which is a gap given that some of these archetypes have equally acute or more acute concentration risk than leading-edge logic. The 2021–2022 automotive chip shortage was a mature-node crisis, not a leading-node crisis.

Operator Landscape Observation

Across the twelve archetypes, the operator concentration varies substantially. Leading-edge logic is a three-operator market (TSMC, Samsung, Intel). DRAM is also three-operator Western plus a scaling Chinese entrant. 3D NAND has four-to-five major operators. SiC has six-to-eight depending on how regional players are counted. Analog is a TI-ADI duopoly for precision analog with many specialty players. CIS is Sony-dominant with Samsung second. MEMS is the most fragmented archetype with a dozen significant operators. Rad-hard is the most regulated archetype with DMEA Trusted Foundry accreditation gating the entire customer base.

This operator-concentration variation explains why some archetypes (leading-edge logic, rad-hard) are easy to map at the operator level — the full operator list is short — while others (MEMS, mature logic, analog) require archetype-specific deep dives because the operator landscape is broader and more fragmented. Each grandchild archetype page provides the operator-level detail appropriate to that archetype's competitive structure.

Fab Inventory

The comprehensive inventory of individual wafer fabs — approximately 100+ facilities globally across the twelve archetypes — is maintained as the Fab Facilities dataset with per-fab profile pages. The dataset is accessible via the Fab Facilities hub and will be organized into archetype-filtered views on the grandchild pages as they come online. Each fab profile page carries identity (operator, location, geopolitical classification), capability (process nodes, wafer size, capacity), status (construction, ramp, volume production), customer relationships, and strategic framing (CHIPS Act / EU Chips Act participation, supply chain positioning).

Related Coverage

Parent: Fab Facilities

Peer facility types: Packaging & Test Facilities · Standalone Test Houses

Archetype child pages (planned): Leading-Edge Logic · Mature Logic · DRAM · 3D NAND · SiC Power · GaN Power & RF · Analog & Mixed-Signal · CMOS Image Sensor · MEMS · III-V Compound Semiconductor · Silicon Photonics · Rad-Hard & Rad-Tolerant

Related fab topics: Process Nodes · Wafer Fab Equipment · Fab Operations

Strategic framing: Bottleneck Atlas · U.S. Reshoring