US Semiconductor Reshoring

The US makes leading-edge wafers again, but none of the new memory and almost none of the advanced packaging an AI chip needs.

Of the 50 US chip plants in the SemiconductorX fab dataset, 32 run at volume. Three of nine leading-edge logic sites run, while all three new DRAM fabs and four of five advanced packaging and test sites are still being built. Of the 80 supplier links behind 10 tracked AI chips, one runs in the US, and only in part.

US chip plants in the SemiconductorX fab dataset by type and US production status. Of 50 US plants, 32 run at volume today. Three of nine leading-edge logic sites run (TSMC Fab 21 phase 1, Intel Fab 52 and Intel D1X); none of the three new memory fabs runs yet; one of five advanced packaging and test sites runs (Intel Fab 9). Analog, mature logic and power and RF plants mostly run today. US CHIP PLANTS BY TYPE: ONE SQUARE PER PLANT Leading-edge logic 3 OF 9 RUNNING Memory 0 OF 3 RUNNING Advanced packaging and test 1 OF 5 RUNNING Analog 6 OF 7 RUNNING Mature and specialty logic 11 OF 12 RUNNING SiC, GaN and RF 9 OF 12 RUNNING Sensors and MEMS 2 OF 2 RUNNING Running at volume Some US volume Being built or planned SEMICONDUCTORX FAB DATASET, 50 US PLANTS, OCTOBER 2026
US plants in dataset
50
Running at volume
32
Leading-edge running
3 of 9
New DRAM running
0 of 3
AI chip links in US
1 of 80
Hub
Supply Chain

Leading-edge logic

Three of Nine Leading-Edge Sites Run Today

The US makes leading-edge logic wafers at volume again, at three sites. TSMC Fab 21 phase 1 in Phoenix has run TSMC's N4 process since the fourth quarter of 2024, Intel Fab 52 in Chandler reached high-volume Intel 18A production in October 2025, and Intel D1X in Hillsboro, Oregon develops Intel's next nodes on ASML High-NA EUV scanners.

Six more leading-edge sites are being built: TSMC Fab 21 phases 2 and 3 (N3 in the second half of 2027, then N2 and A16), Intel Fab 62 in Chandler, Intel Ohio One, Samsung Taylor (2nm, volume in 2027) and the Terafab Production Fab in Grimes County, Texas. Node detail for each is at Leading-Edge Logic Fabs and Process Nodes.

The rest of the US base is older and already running: 6 of 7 analog plants, most of them Texas Instruments 300mm fabs, and almost all the mature-logic, power and RF plants in the dataset make chips in the US today.

Memory and packaging

Memory and Packaging Arrive Last

An AI accelerator is a logic die, stacks of high-bandwidth memory (HBM) and an advanced package that joins them. The US has the first of the three. None of the three new US DRAM fabs runs yet, and of five advanced packaging and test sites only Intel Fab 9 in New Mexico runs, packaging Intel's own products. So NVIDIA Blackwell wafers made in Arizona still go back to Taiwan for CoWoS packaging (NVIDIA spotlight).

When the missing pieces of a US-made AI chip arrive. Leading-edge logic wafers run in Arizona since late 2024 and 2025. The first US DRAM wafers from Micron Boise are due in mid-2027, Amkor Peoria packaging in early 2028, TSMC Arizona packaging before 2029 and SK hynix HBM packaging in Indiana in the second half of 2029. Dates after October 2026 are company targets. WHEN EACH PIECE OF A US-MADE AI CHIP ARRIVES (COMPANY TARGETS AFTER OCTOBER 2026) 2024 2025 2026 2027 2028 2029 2030 2031 TODAY TSMC Fab 21 phase 1: N4 logic Intel Fab 52: Intel 18A logic Samsung Taylor: 2nm logic volume Micron Boise ID1: first DRAM wafers TSMC Fab 21 phase 2: N3 volume Amkor Peoria: advanced packaging Micron Boise ID2: DRAM and HBM TSMC Arizona packaging (CoWoS) SK hynix West Lafayette: HBM packaging Intel Ohio One: first fab Micron Clay: first DRAM fab Logic wafers Memory Packaging Running Target date
Logic arrives first, memory and packaging two to three years later. Dates after October 2026 are company targets. Sources: company announcements; Congressional Research Service R49031 (July 2026).

By state

Texas and Arizona Hold Most of the New Capacity

Texas has the most US chip plants in the dataset and Arizona the most new ones. Texas mixes a leading-edge foundry, the largest US analog campus, a 14nm to 65nm Samsung foundry in Austin and a captive AI chip program. Arizona is where leading-edge logic and the first US advanced packaging for AI chips are being built side by side. Reasons the two states draw this capacity are worked through on AustinIO at Why Texas. One Texas proposal is not in the count yet: Substrate Project Factory One, a fab of at least $10 billion proposed for the Texas A&M RELLIS campus in Bryan to run the startup's own X-ray lithography tools, with no construction start announced.

US chip plants in the SemiconductorX dataset by state, split into running and planned. Texas has 10 plants, eight running. Arizona has eight, three running and five being built, the largest share of new capacity in any state. US CHIP PLANTS BY STATE, RUNNING AND PLANNED (TOP 12 STATES) Texas 8 running, 2 planned Arizona 3 running, 5 planned California 4 running, 0 planned Idaho 1 running, 2 planned New York 2 running, 1 planned North Carolina 2 running, 1 planned Oregon 3 running, 0 planned Vermont 3 running, 0 planned Minnesota 2 running, 0 planned Utah 1 running, 1 planned Colorado 1 running, 0 planned Indiana 0 running, 1 planned ONE BLOCK PER PLANT. SEMICONDUCTORX FAB DATASET, OCTOBER 2026
Running includes plants with some US volume. Source: SemiconductorX fab dataset.
Largest US fab projects by state
StatePlantsWhat they makeStatus
TexasSamsung Taylor (2nm foundry); Texas Instruments Sherman SM1 and Richardson RFAB1 and RFAB2 (Sherman cluster); Samsung Austin S2; NXP Austin; Terafab (Grimes County)2nm logic; 300mm analog; 14nm to 65nm foundry; automotive MCUs; captive AI chipsTI SM1 in volume since December 2025; Samsung Taylor volume 2027; Terafab limited operations targeted late 2027
ArizonaTSMC Fab 21 phases 1 to 3 and two packaging plants; Intel Fab 52 and Fab 62; Amkor PeoriaN4, N3, N2 and A16 logic; Intel 18A; CoWoS and advanced packagingTSMC phase 1 since Q4 2024; Intel Fab 52 since October 2025; TSMC phase 2 second half 2027; Amkor early 2028
New YorkMicron Clay; GlobalFoundries Fab 8, MaltaDRAM; specialty logic, silicon photonics and GaNGlobalFoundries running; Micron Clay first fab Q3 2030
IdahoMicron Boise ID1 and ID2Leading-edge DRAM; HBM in ID2ID1 first wafers mid-2027; ID2 late 2028
OhioIntel Ohio One, New AlbanyIntel 14AFirst fab 2030 to 2031; second fab 2032
OregonIntel D1X, Hillsboro; Analog Devices BeavertonIntel process development with High-NA EUV; analogRunning
UtahTexas Instruments Lehi LFAB1 and LFAB2300mm analogLFAB1 running; LFAB2 under construction
IndianaSK hynix West LafayetteHBM stacking and test for wafers made in KoreaGround broken August 2026; volume second half 2029
New MexicoIntel Fab 9, Rio RanchoFoveros 3D packaging for Intel productsRunning since 2024

Timeline

Most Dates Have Slipped Two to Five Years

Of the large projects, only TSMC Arizona Fab 2 has moved earlier, pulled forward by AI demand. Micron Clay moved from 2028 to the third quarter of 2030 after its wetlands review, Intel Ohio from 2025 to 2030 to 2031, and Amkor from 2027 to 2028 after moving its site. The Congressional Research Service counts the last contracted CHIPS milestone in 2033. What slows each project is ranked at Sovereignty Constraints.

US fab milestones, achieved and targeted
DateProjectLocationMilestone
Q4 2024 (achieved)TSMC Fab 21 phase 1Phoenix, ArizonaN4 volume production
May 2025 (achieved)GlobalWafers AmericaSherman, TexasFirst US plant for 300mm silicon wafers opens
October 2025 (achieved)Intel Fab 52Chandler, ArizonaIntel 18A high-volume production
December 2025 (achieved)Texas Instruments SM1Sherman, Texas300mm analog volume production
2027Samsung TaylorTaylor, Texas2nm volume for Tesla and others; initially 2024
Mid-2027Micron ID1Boise, IdahoFirst DRAM wafer output
Second half 2027TSMC Fab 21 phase 2Phoenix, ArizonaN3 volume; once delayed, then pulled forward a year
Late 2027Terafab Production FabGrimes County, TexasLimited operations (SpaceX target)
Early 2028Amkor ArizonaPeoria, ArizonaPackaging and test; initially 2027, site moved
Late 2028Micron ID2Boise, IdahoFirst wafers, including HBM
Second half 2029SK hynix West LafayetteWest Lafayette, IndianaHBM packaging volume
2030 to 2031Intel Ohio OneNew Albany, OhioFirst fab; initially 2025, at risk without a 14A customer
Q3 2030Micron ClayClay, New YorkFirst fab; initially 2028; four-fab buildout runs to 2041

AI chips

One of 80 AI Chip Supply Links Runs in the US

The site tracks the supply ring of 10 AI chips, from NVIDIA Rubin to Huawei Ascend 910C: 80 links from logic die to final test. One link runs in the US: the B300 logic die, made in part at TSMC Fab 21 in Arizona since October 2025 and sent back to Taiwan for packaging. Four more are planned. Everything else is made abroad, mostly in Taiwan and South Korea (Chip Supplier Rings).

  • Made in US
  • Some US volume
  • US planned
US links in the supply rings of 10 AI chips
ChipComponentUS plantUS status
NVIDIA Blackwell Ultra B300Logic dieTSMC Arizona, Fab 21, PhoenixSome US volume
NVIDIA RubinFinal testKYEC (US site)US planned
Tesla AI5Logic dieSamsung Foundry, Taylor fab, Taylor, TXUS planned
Tesla AI5Logic dieTSMC, Fab 21 Arizona and Taiwan fabs, Phoenix, AZUS planned
SK hynix HBM4 12-highAdvanced packagingSK hynix, West Lafayette plant, West Lafayette, INUS planned

Record

Page Record

Covers
US chip plants by type, status and state; the order in which logic, memory and packaging arrive; milestone dates; US links in AI chip supply rings
Sources
SemiconductorX fab dataset and chip supply ring dataset (October 2026); Congressional Research Service R49031 (July 14, 2026); GAO-26-109121 (August 6, 2026); TSMC, Intel, Micron, Samsung, SK hynix, Amkor and Texas Instruments announcements.
Last verified
October 2026