Photolithography Step



Photolithography is the most critical and capital-intensive step in semiconductor manufacturing. It defines the physical dimensions of features on the wafer using light-sensitive materials and masks. As chips scale below 10nm, photolithography has become a strategic chokepoint—both technically and geopolitically. This page explains the key equipment types, processes, materials, vendors, and future trends related to lithography, with a special emphasis on EUV.

Photolithography is a pattern transfer process that uses light to expose a photoresist layer on the wafer. This defines the microscopic geometries of the integrated circuit. Each layer of a chip may require its own unique lithography step, making this process one of the most repetitive and expensive in a modern fab.

Photolithography accounts for the largest share of wafer fab equipment (WFE) spend. EUV adoption is accelerating, with High-NA EUV tools expected in HVM by ~2025–2026. Alternatives such as directed self-assembly (DSA) and nanoimprint lithography remain in research but are unlikely to displace EUV for leading-edge logic and memory.


Core Photolithography Workflow

Transfer circuit patterns layer by layer to define transistor and interconnect geometries. This process step is repeated 30 - 50+ times per wafer depending on device complexity.

Step Description
1. Wafer Cleaning Removes particles and organic contaminants before resist application
2. Photoresist Coating Spin-coated resist layer applied with precise thickness control
3. Soft Bake Removes solvents from resist to improve adhesion and resolution
4. Exposure Light shines through a photomask mask to expose the photoresist pattern
5. Post-Exposure Bake Stabilizes latent image and prepares resist for development
6. Development Removes exposed or unexposed areas depending on resist type
7. Hard Bake Final curing step to improve resist durability for etch*

* - right after the hard bake, there are etch (pattern transfer) or ion implant (for doping layers) plus resist strip/clean steps that are performed to complete each layer, but these are not considered part of the photolithography process.


Types of Lithography Systems

System Type Wavelength Resolution Node Use Case Status
DUV Lithography (ArF / KrF / i-Line) 193nm / 248nm / 365nm ~90–30nm Used in legacy, analog, power ICs, FEOL/BEOL layers in 28nm+ Mature, widely deployed
Immersion DUV (ArFi) 193nm (with liquid immersion) ~28–14nm Used in 28nm to 7nm nodes (multiple patterning) Workhorse for pre-EUV nodes
EUV Lithography 13.5nm ~13–8nm native; sub-5nm with multipatterning 5nm, 3nm, 2nm logic; DRAM trenches In volume production (ASML NXE series)
High-NA EUV 13.5nm (NA = 0.55) 2nm and below with better LER/CD control Planned for 2nm and beyond (Intel, TSMC roadmaps) Pre-production (ASML EXE series)
Direct Write E-Beam Variable (electron beam) Sub-10nm with no mask ASICs, R&D, low-volume patterning Slow, niche tool

Photomask & Reticle Supply Chain

Provide the master pattern transferred onto the wafer.

Component Description Strategic Vendors
Photomask Quartz or glass plate with opaque chrome patterns Photronics, Toppan, Hoya, DNP
Pellicle Protective membrane that prevents particles on mask Mitsui Chemicals, EUV pellicle R&D ongoing
Mask Writer E-beam tool that writes mask pattern with nanometer precision NuFlare, IMS Nanofabrication, Vistec
Mask Inspection Detects defects before masks go into production KLA, Lasertec

Critical Vendors in the Lithography Ecosystem

Segment Key Players Notes
EUV Scanners ASML Monopoly supplier of EUV litho tools (NXE, EXE lines)
Optics Carl Zeiss SMT Provides EUV mirrors, lenses, alignment systems
Laser Sources Trumpf, Gigaphoton High-power CO2 lasers drive EUV plasma generation
Photoresists JSR, Tokyo Ohka Kogyo, Fujifilm Resist R&D is critical for EUV resolution and LER

Strategic & Technical Challenges

Challenge Why It Matters
Cost per Tool EUV scanners cost over $150M; few companies can afford them
Mask 3D Effects EUV masks have multi-layer reflectors, increasing pattern distortion
Pellicle Maturity Current EUV pellicles degrade quickly, limiting throughput
Source Power Higher wattage needed to boost wafer-per-hour throughput
Geopolitical Risk EUV exports restricted to China; supply chain tightly controlled by U.S./EU allies

Process Consumables

  • Photoresists: Light-sensitive polymers (positive, negative, chemically amplified, EUV-specific). Supplied by JSR, TOK, Shin-Etsu, DuPont, Merck.
  • Developers: Typically TMAH aqueous solutions; dissolve exposed or unexposed resist regions.
  • Anti-Reflective Coatings (ARC/BARC): Prevent standing wave effects during exposure.

Cleanroom & Environment

  • Photolithography bays are among the cleanest areas in a fab - typically Class 1 or better.
  • Environmental control includes vibration isolation, temperature ±0.1 °C, humidity ±1%.
  • Airborne molecular contamination (AMC) monitoring is critical for EUV resists and masks.


Future Directions in Lithography

While EUV and High-NA EUV represent the mainstream path for advanced nodes, research continues into alternative or complementary lithography approaches. These methods aim to extend patterning beyond the physical limits of optics or reduce overall process complexity and cost.

  • Directed Self-Assembly (DSA): Uses block copolymers that naturally form nanoscale patterns. Potential for sub-10 nm features but integration with existing fab processes remains difficult.
  • Computational Lithography: Uses AI/ML to simulate distortions and correct patterns pre-print.
  • Nanoimprint Lithography (NIL): Directly embosses a pattern into a resist layer using a physical template. Attractive for simplicity and low cost, but defectivity and template durability are significant challenges.
  • Maskless Lithography: Employs electron-beam or multi-beam direct-write systems to eliminate photomasks. Excellent resolution but extremely slow throughput, currently limited to photomask production and R&D.
  • Advanced EUV Resists: Novel metal-oxide and molecular resists designed to overcome stochastic variation and line-edge roughness at sub-2 nm nodes.
  • Hybrid Approaches: Combinations of High-NA EUV with DSA or NIL could enable further scaling while reducing multi-patterning steps.

Although none of these alternatives are likely to replace EUV in high-volume manufacturing in the near term, they remain active areas of R&D that may find application in niche or next-generation processes.