Photolithography

Track and scanner · DUV, EUV and High-NA EUV · one pass per mask layer

Every patterned layer of every chip starts on a lithography scanner, and the most advanced layers can be printed only on an ASML EUV tool. ASML shipped 44 low-NA EUV scanners in 2025 and expects about 65 in 2026; that output caps how fast the world adds leading-edge capacity, and none of it goes to China.

ASML shipped 44 low-NA EUV scanners in 2025 and expects about 65 in 2026. Only ASML builds EUV scanners. Nikon also builds ArF immersion scanners, Canon builds KrF and i-line tools, and China's SMEE builds dry ArF, KrF and i-line tools with immersion in development. LOW-NA EUV SCANNERS SHIPPED BY ASML 2025 44 2026 ~65 expected PLUS HIGH-NA EUV: ONE SYSTEM SOLD IN 3Q 2026. WHO BUILDS EACH CLASS OF SCANNER ASML Nikon Canon SMEE CHINA High-NA EUV 13.5 NM, 0.55 NA EUV 13.5 NM, 0.33 NA ArF immersion 193 NM IN WATER ArF dry and KrF 193 AND 248 NM i-line 365 NM SOLID: SHIPPING. HALF: KrF ONLY. DASHED: IN DEVELOPMENT. SOURCE: ASML 3Q 2026 CALL.
EUV maker
ASML only
EUV shipped, 2025
44
EUV expected, 2026
~65
High-NA first node
Intel 14A
EUV in China
None
Hub
Process

One pass

Every Patterned Layer Starts With a Lithography Pass

A leading-edge logic wafer goes through 80 to 100 lithography passes, one for each mask layer.

Photolithography copies a pattern from a photomask onto the wafer. The scanner projects the mask image, shrunk four times, onto a thin film of photoresist; development washes away the exposed (or unexposed) resist; and the remaining resist shields the film below while etch or ion implantation transfers the pattern. Every patterned layer of every chip starts with one of these passes.

One lithography pass. On the coater-developer track the wafer is primed, coated with resist and soft baked. It moves to the scanner for alignment and exposure, then back to the track for the post-exposure bake, development and hard bake. Etch or implant then transfers the pattern, and the resist is stripped. TRACK Prime HMDS Coat SPIN Soft bake DRY SCANNER Align OVERLAY Expose MASK IMAGE TRACK PEB ACID Develop TMAH Hard bake Etch or implant THEN STRIP THE RESIST ONE PASS PER MASK LAYER; A LEADING-EDGE LOGIC WAFER RUNS 80 TO 100 OF THEM. TRACK AND SCANNER ARE LINKED; THE WAFER MOVES BETWEEN THEM WITHOUT LEAVING THE CLUSTER.

A pass runs on two linked machines: a coater-developer track, almost always from Tokyo Electron, and a scanner from ASML, Nikon or Canon. The track handles everything wet and hot; the scanner only aligns and exposes. Because the scanner is the most expensive tool in the fab, the line is laid out around keeping it busy, and lithography throughput sets how many wafers a fab can start. Resist chemistry, development and strip are covered on Photoresist and Development.

Wavelength

Wavelength and Aperture Set the Smallest Line

Smallest printable half-pitch in a single exposure, computed from the Rayleigh criterion with k1 of 0.3: KrF about 80 nm, ArF dry about 62 nm, ArF immersion about 43 nm, EUV about 12 nm, High-NA EUV about 7 nm. SINGLE-EXPOSURE HALF-PITCH = k1 x WAVELENGTH / NA, WITH k1 = 0.3 (COMPUTED) KrF 248 NM, NA 0.93 ~80 nm ArF dry 193 NM, NA 0.93 ~62 nm ArF immersion 193 NM, NA 1.35 ~43 nm EUV 13.5 NM, NA 0.33 ~12 nm High-NA EUV 13.5 NM, NA 0.55 ~7 nm PRODUCTION LINES PRINT BELOW THESE PITCHES ONLY BY SPLITTING A LAYER ACROSS SEVERAL EXPOSURES.
Lithography generations
GenerationLight sourceTypical node rangeWhere it is used
i-lineMercury lamp, 365 nm350 nm and coarserThick-resist and non-critical layers, power, MEMS, packaging
KrFKrypton fluoride excimer laser, 248 nm250 to 130 nm nodesMature-node logic, analog and many memory layers
ArF dryArgon fluoride excimer laser, 193 nm90 to 65 nm nodesMid-range logic and memory layers
ArF immersion (ArFi)193 nm through a water film, NA up to 1.3545 nm nodes, and down to 7nm-class with multi-patterningThe workhorse for critical layers from 45nm to 7nm, and many non-critical layers below
EUVTin plasma, 13.5 nm, NA 0.337nm-class nodes and belowCritical layers at TSMC N5 and below, Samsung, Intel 4 and later, and advanced DRAM
High-NA EUV13.5 nm, NA 0.55, anamorphic opticsBelow 2nm-class nodes; about 8 nm half-pitch (ASML)Intel 14A; Samsung and TSMC later in the decade

Resolution scales with wavelength divided by numerical aperture (NA). Water raised ArF's NA from 0.93 to 1.35 and bought two node generations; EUV cut the wavelength 14-fold. Most chips still use all of these: an N3 wafer is exposed with EUV on its critical layers and ArFi, ArF and KrF on the rest.

Multi-patterning

Multi-Patterning Buys Density With Extra Steps

Self-aligned quadruple patterning with ArF immersion turns one printed line into four by depositing and etching spacers twice. An EUV scanner prints the same pitch in one exposure. ONE TIGHT-PITCH LAYER, TWO WAYS Print ArFi, 4x PITCH Spacer 1 DEPOSIT AND ETCH Spacer 2 REPEAT Result 4 LINES PER PRINT EUV ONE EXPOSURE, SAME PITCH EACH SPACER LOOP ADDS DEPOSITION, ETCH, CLEAN AND METROLOGY STEPS AND A CHANCE OF PITCH WALK. CHINA'S 7NM-CLASS LINES WORK THIS WAY, WITHOUT EUV. NOT TO SCALE.

Below about 40 nm half-pitch, ArFi needs more than one pass per layer. Litho-etch-litho-etch (LELE) splits a layer into two masks; self-aligned double and quadruple patterning (SADP and SAQP) use deposited spacers to halve or quarter the printed pitch. Each split adds deposition, etch, clean and metrology steps, adds overlay error, and lengthens cycle time.

EUV replaced three or four ArFi exposures on the tightest layers at 7nm and 5nm, which is why foundries paid for it. The trade continues: at 2nm, some EUV layers need double patterning themselves, the opening High-NA EUV is built to close.

Scanner supply

One Scanner Maker Sets the Pace

ASML is the only company that builds EUV scanners. It shipped 44 low-NA EUV systems in 2025 and expects about 65 in 2026, with EUV sales up more than 45% and total sales guided to €44 billion to €45 billion. It is adding about 30% more low-NA EUV and DUV immersion capacity for 2027, says that still will not meet demand for 2027 and 2028, and is fielding orders for 2029 and 2030. Its next low-NA model, the NXE:3800F, ships in small numbers in early 2027.

  • Made in US
  • Some US volume
  • US planned
  • Made abroad
Scanner makers and their critical suppliers
SiteLocationMakesStatusUS status
ASML VeldhovenVeldhoven, NetherlandsEUV and DUV scanner integration and testOperating; low-NA EUV and DUV immersion capacity growing about 30% for 2027Made abroad
ASML San Diego (Cymer)San Diego, CAEUV light sources and DUV excimer lasersOperatingMade in US
ASML WiltonWilton, CTReticle stages and handling modules for EUV and DUV scannersOperatingMade in US
Carl Zeiss SMTOberkochen, GermanyEUV mirrors and DUV lenses; sole optics source for ASMLOperatingMade abroad
TrumpfDitzingen, GermanyCO2 drive lasers for the EUV plasma sourceOperatingMade abroad
NikonKumagaya and Yokohama, JapanArF immersion, ArF, KrF and i-line scannersOperatingMade abroad
CanonUtsunomiya, JapanKrF and i-line steppers and scanners; nanoimprint lithographyOperatingMade abroad
SMEEShanghai, ChinaDry ArF, KrF and i-line scannersOperating; immersion in developmentMade abroad
Placeholder: other scanner subsystem suppliers (VDL ETG frames, Berliner Glas, Gigaphoton excimer lasers)

The scanner is the visible end of a supply chain that is concentrated at every layer. Zeiss is the only source of EUV mirrors; Trumpf builds the drive lasers; the EUV light source itself is built by ASML's Cymer unit in San Diego, the largest piece of an EUV scanner made in the United States. The tool makers and their subsystems are covered on Lithography Equipment and ASML EUV Scanner.

High-NA EUV

High-NA EUV Is an Intel Bet This Decade

High-NA EUV adoption
ChipmakerStatusFirst volume use
IntelEXE:5000 and EXE:5200B at Hillsboro, Oregon; more than one million wafers exposed (ASML, October 2026)Intel 14A
SamsungSystems installed for developmentHigh-volume use planned for 2028 (ASML)
TSMCEvaluating; prints A16 and A14 with low-NA EUVHigh-volume use planned for 2030 (ASML)
SK hynixSystem installed at Icheon for DRAM development (reported)Not announced

High-NA EUV raises NA from 0.33 to 0.55 and prints about 8 nm half-pitch in one exposure. The cost is a smaller exposure field: anamorphic optics halve the field in one direction, so a die larger than about 429 mm2 must be stitched from two exposures, and each tool costs well above a low-NA scanner. ASML sold one High-NA system in the third quarter of 2026 and reports fleet availability approaching 90%. Intel is the only chipmaker committed to it for a production node this decade.

China

China Is Cut Off at EUV

No EUV scanner has ever been shipped to China. Dutch export rules, coordinated with US controls, bar EUV sales, and licenses are required for the most advanced ArFi models. China is still about 20% of ASML's 2026 sales, almost all in DUV tools for mature-node fabs.

  • Multi-patterning instead of EUV: SMIC's 7nm-class N+2 process, which makes Huawei's Kirin and Ascend chips, uses ArFi with multi-patterning. It works, at lower yield and more passes per layer than an EUV flow.
  • Domestic scanners: SMEE in Shanghai builds dry ArF, KrF and i-line scanners; its immersion tool is still in development.
  • EUV prototype: Reuters reported in December 2025 that a prototype EUV machine in a guarded Shenzhen lab, linked to Huawei, generates EUV light but has not produced working chips; the target for chips is 2028, and Reuters' sources judged 2030 more realistic. The optics are the main obstacle, since only Zeiss makes EUV mirrors.

China's node ceiling is covered on Process Nodes.

Masks and resist

Masks and Resist Feed Every Exposure

  • Photomasks: each layer needs a mask; a leading-edge logic product uses 80 to 100. EUV masks are reflective multilayer blanks, made by HOYA and AGC, with pellicles from Mitsui Chemicals. See Photomasks and Reticles and EUV Mask Blanks and Pellicles. ASML and TSMC are developing a larger 12-inch EUV mask format, with a pilot line targeted for 2031.
  • Photoresist: each wavelength has its own resist chemistry, almost all from Japanese suppliers. See Photoresist and Development.
  • Nanoimprint: Canon's FPA-1200NZ2C presses the pattern into resist with a mold instead of light. It shipped its first system to the Texas Institute for Electronics in Austin in 2024; it is in use for memory development, not volume logic.

Record

Page Record

Covers
The lithography pass, wavelength generations, multi-patterning, scanner supply, High-NA EUV adoption, China's position, masks and resist
Sources
ASML third-quarter 2026 results and call (October 14, 2026); ASML 2025 annual results (January 2026); Reuters via TechRepublic (Shenzhen EUV prototype, December 2025); ASML, Canon and Nikon product pages; half-pitch values computed from the Rayleigh criterion
Last verified
October 2026