Wafer Slicing | SemiconductorX

Wafer slicing converts a cylindrical crystal ingot into thin disc-shaped substrates -- the wafers shipped to semiconductor fabs. The ingot is first trimmed and ground to the target diameter, then sliced by a wire saw into wafers of precise thickness. Slicing introduces mechanical stress and surface damage that must be removed by subsequent lapping, etching, and polishing steps. The two key economic variables in slicing are kerf loss (silicon consumed as sawdust) and wafer flatness (bow and warp), which determine downstream polishing yield and ultimately the fraction of usable prime wafers per ingot.

Slicing Technology: Diamond Wire vs Slurry Wire

Parameter	Diamond Wire Saw	Slurry Wire Saw (legacy)
Abrasive	Diamond particles electroplated or resin-bonded directly onto wire	Silicon carbide abrasive particles suspended in polyethylene glycol slurry, delivered by wire
Kerf loss	~100-130µm per cut	~150-200µm per cut
Wire diameter	~70-120µm; thinner wire = less kerf loss	~120-160µm + slurry thickness
Cutting speed	Higher; 20-30m/min wire speed	Lower; slurry viscosity limits speed
Surface damage	Shallower subsurface damage; less lapping required	Deeper subsurface damage layer; more aggressive lapping needed
Environmental	Cleaner; water-based coolant; no SiC slurry waste	SiC + PEG slurry requires treatment and disposal
Cost	Higher wire cost per unit; lower total cost through throughput and reduced downstream processing	Lower wire cost; higher consumable (slurry) cost and processing cost
Industry status	Dominant for silicon; standard at all leading wafer manufacturers	Legacy; effectively displaced by diamond wire for silicon production

Key Slicing Parameters

Parameter	Typical Value (300mm silicon)	Impact
Target thickness	~775µm as-sliced; ~725µm after polishing	Balance between mechanical strength and silicon material use; thinner wafers under development to improve material efficiency
Kerf loss	~100-150µm per cut (diamond wire)	Silicon lost as kerf dust is unrecoverable; at 100µm kerf from a 300mm ingot, approximately 12% of ingot volume is lost to sawing -- a significant cost driver at polysilicon prices
Bow	<60µm as-sliced; <30µm after lapping	Bow is the deviation of the wafer median surface from a reference plane; excessive bow causes focus issues in lithography and handling problems in automated equipment
Warp	<50µm as-sliced	Total range of deviation of the median surface; affects wafer chuck contact uniformity in lithography and etch tools
Total thickness variation (TTV)	<5µm as-sliced; <1µm after double-side grinding	Thickness non-uniformity across the wafer; tight TTV is prerequisite for sub-nm flatness after CMP

Equipment Suppliers

Wire saw equipment for semiconductor wafer slicing is a concentrated market. Disco Corporation (Japan) is the leading supplier of precision dicing and slicing equipment for semiconductor wafers, with a dominant market position in wafer dicing saws (back-end) and significant presence in wire slicing systems. Meyer Burger Technology (Switzerland) developed advanced diamond wire saw systems and was a key supplier to the photovoltaic silicon wafer market, with technology also applied to semiconductor-grade silicon. The two dominant wire saw suppliers for semiconductor wafer production are Takatori (Japan) and Komatsu NTC (Japan), which supply multi-wire saws used by Shin-Etsu, Sumco, Siltronic, and GlobalWafers. NuFlare and Accretech (Tokyo Seimitsu) supply complementary metrology and edge grinding equipment used in the ingot-to-wafer preparation flow.

SiC Slicing: A Different Challenge

SiC is approximately 9.5 on the Mohs hardness scale -- harder than almost any industrial abrasive except diamond. Slicing 4H-SiC boules requires diamond wire saws specifically engineered for the material's hardness, with wire tensions, feed rates, and coolant chemistries different from silicon. SiC slicing is significantly slower than silicon slicing: kerf loss per cut is higher (~200-300µm versus ~100-150µm for silicon), wire wear is faster, and the as-sliced surface requires more aggressive grinding and polishing to reach the subsurface damage removal required for epi-ready surface quality. The slicing step is one contributor to SiC substrate's cost premium over silicon. An alternative approach under development is laser slicing (cold-split or stealth dicing technology), which uses laser-induced internal stress to crack SiC along a crystallographic plane with reduced kerf loss -- but this technology is not yet in volume production for full boule slicing.

Supply Chain Outlook

Diamond wire saw technology is mature for silicon and will not change structurally -- the ongoing engineering effort focuses on reducing wire diameter (thinner kerf, less silicon loss) and improving wire life (lower consumable cost). The SiC slicing challenge is an active area: as SiC substrate demand grows and the 200mm transition requires slicing larger-diameter boules, slicing throughput and kerf economics become more consequential. Laser cold-split technology, if it reaches production viability at 200mm, could meaningfully improve SiC substrate yield per boule and reduce substrate cost.