Design partners
Hyperscaler Chips Run Through a Few Design Partners
An application-specific IC (ASIC) fixes its logic at tape-out, so it does one job at the best performance per watt and cannot be reprogrammed.
Hyperscalers write the architecture and hand physical design, packaging and foundry management to a partner. Broadcom works with Google on TPU, with Meta on MTIA and with OpenAI, which in October 2025 announced 10 gigawatts of Broadcom-built accelerators. Marvell designed AWS Trainium2; Alchip is reported on Trainium3, GUC on Microsoft Maia and MediaTek on some TPU variants. Every one of these chips is made at TSMC.
ASIC families
ASIC Families, Products and Process
| Domain | Products | Process | Supplier and position |
|---|---|---|---|
| Broadcom networking | Tomahawk 6 (102.4 Tbps switch); Jericho3-AI and Jericho4 for AI cluster fabrics; Trident for enterprise | TSMC 3nm (Tomahawk 6); TSMC 5nm | Broadcom, fabless; the leading merchant data center switch silicon |
| Marvell networking and custom | Teralynx switches; OCTEON DPUs; custom AI and CPU chips for cloud customers | TSMC 3nm and 5nm | Marvell, fabless; designed AWS Trainium2 |
| Custom AI chips (hyperscaler) | Google TPU, Meta MTIA, OpenAI accelerator, AWS Trainium, Microsoft Maia | TSMC 3nm and 5nm | Designed in-house with Broadcom, Marvell, Alchip, GUC or MediaTek; captive, not sold on the open market |
| Custom CPUs (hyperscaler) | AWS Graviton; Microsoft Cobalt; Google Axion | TSMC 5nm and 3nm | In-house Arm designs; see CPUs |
| Vision and driver-assist ASICs | Ambarella CV3-AD and CV5 families | Samsung 5nm (CV3-AD) | Ambarella, fabless; competes with NVIDIA DRIVE for car domain controllers |
| Phone modems | Qualcomm Snapdragon X-series; Apple C1; MediaTek; Samsung Exynos Modem | TSMC 4nm class; Samsung 4nm | Qualcomm leads premium modems; Apple began replacing Qualcomm with its own C1 in 2025 |
| China | HiSilicon Balong modems and Ascend; Sophgo; Zhaoxin | SMIC | Restricted from TSMC leading edge since 2020 for Huawei |
Build or buy
Custom Silicon Pays Only at Hyperscaler Volume
A full tape-out at 5nm or 3nm, with EDA licenses, SerDes and memory interface IP, masks and verification, costs hundreds of millions of dollars and takes 18 to 24 months to first silicon. That cost confines leading-edge ASICs to companies that deploy chips by the hundreds of thousands, or that sell them to many customers, as Broadcom and Marvell do with switch silicon.
ASICs win when the workload is stable and the volume high, so the power saved over a GPU repays the design cost. They lose when models change faster than an 18-month design cycle. FPGAs often prototype a function that an ASIC later fixes in silicon; see FPGAs.
Bottlenecks
ASIC Supply Chain Bottlenecks
| Bottleneck | Affects | Severity |
|---|---|---|
| TSMC 3nm and 5nm wafers | Merchant switch ASICs, every hyperscaler chip, NVIDIA and AMD GPUs | Critical: captive chip demand is hidden from market data |
| Design-partner concentration | Hyperscalers without full in-house physical design teams | Medium-high: Broadcom alone carries Google, Meta and OpenAI programs |
| EDA duopoly | Every advanced-node tape-out (Synopsys, Cadence) | Structural; US EDA export rules hit Chinese ASIC programs |
| CoWoS and ABF substrates | Multi-die AI and networking ASICs | High: same packaging pool as GPUs |
Record
Page Record
- Covers
- Merchant and custom ASICs, hyperscaler design partners, NRE economics and supply risk
- Sources
- Broadcom fiscal Q3 2026 results (September 2026); OpenAI and Broadcom announcement (October 2025); Marvell, Ambarella, Apple and Qualcomm disclosures; press reports on Alchip, GUC and MediaTek programs
- Last verified
- October 2026