Fabs receive wafers in standard diameters, materials, and surface preparations depending on device type (logic, memory, power, RF, photonics). This page summarizes the typical wafer options, epitaxial configurations, mechanical specs, electrical grades, and the front-end carriers/containers used from dock to stock to tool load.
Standard Diameters & Typical Use
| Diameter |
Common Name |
Typical Thickness (mm) |
Primary Uses |
| 100 mm |
4-inch |
0.5–0.7 |
R&D, MEMS, legacy analog/RF |
| 150 mm |
6-inch |
0.6–0.8 |
Power (Si, SiC), RF GaAs, GaN, MEMS |
| 200 mm |
8-inch |
0.7–0.9 |
Mixed-signal, analog, image sensors, SiC power |
| 300 mm |
12-inch |
0.75–1.0 |
Leading-volume logic, DRAM/NAND, some CIS |
| 450 mm |
18-inch |
~1.0 |
Not in production (historical R&D) |
Silicon Wafer Specs (as received)
| Attribute |
Options / Range |
Notes |
| Crystal Orientation |
{100}, {111}, {110} |
{100} mainstream CMOS; {111} MEMS/power; {110} specialty |
| Conductivity Type |
P-type (Boron), N-type (Phosphorus/Antimony/Arsenic) |
Specified by resistivity and dopant |
| Resistivity |
~0.001–>10,000 O·cm |
Low-? for power/RF; high-? for image sensors, SOI handle |
| Surface Finish |
Single-side polished (SSP), Double-side polished (DSP) |
DSP common for 200/300 mm FEOL |
| Edge Features |
Bevel, edge rounding, edge exclusion (typically 2–3 mm) |
Protects from chipping; defines non-process ring |
| Identification |
Laser-marked ID (frontside/backside), Notch (300 mm), Flats (=200 mm) |
Lot/wafer traceability for MES |
| Particle/Cleanliness |
Prime grade, epi-ready, low metals |
Meets incoming QC for FEOL cleaning track-in |
Specialty Silicon Substrates
| Type |
Structure |
Use Cases |
Notes |
| SOI (Silicon-on-Insulator) |
Device Si / BOX (SiO2) / Handle Si |
FD-SOI logic, RF switches, MEMS |
BOX ~10–200 nm; device film 5–200 nm |
| HR-Si (High-Resistivity) |
? > 1 kO·cm |
RF front-ends, low-crosstalk analog |
Lower substrate loss tangent |
| Epi-Ready Prime |
Optimized surface chemistry |
Homoepitaxy for CMOS/power |
Low metallic contamination spec |
Compound & Specialty Wafers
| Material |
Common Diameters |
Typical Orientation |
Primary Applications |
| SiC (Silicon Carbide) |
150, 200 mm |
(0001) 4H-SiC |
Power MOSFETs, diodes, EV inverters |
| GaN on Si / SiC / Sapphire |
150, 200 mm (on Si), 100–150 mm (SiC/Sapphire) |
c-plane (0001) |
RF PAs, power HEMTs, fast chargers |
| GaAs |
100, 150 mm |
(100) 2° off |
PA, switches, optoelectronics |
| InP |
75, 100, 150 mm |
(100) |
Photonic ICs, lasers, high-speed SerDes |
| Sapphire (Al2O3) |
100–200 mm |
a-, c-, r-plane |
LED, GaN templates, optics |
| Fused Silica / Glass |
200–300 mm |
N/A |
Interposers, RF, MEMS |
Epitaxy Options (as delivered)
| Epi Type |
Substrate |
Typical Thickness |
Purpose |
| Silicon Homoepitaxy |
Si |
50 nm–10 µm |
Well/channel engineering, gettering, low-defect device layer |
| SiC Epi |
4H-SiC |
2–20 µm (power) |
Drift layer formation for high-voltage devices |
| GaN Epi (HEMT) |
Si, SiC, Sapphire |
Buffer + GaN ~1–5 µm + AlGaN barrier |
2DEG channel for RF/power HEMTs |
| III-V Photonics |
InP, GaAs |
Multi-quantum-well stacks |
Lasers, modulators, detectors |
| SOI Device Film |
SOI |
5–200 nm |
FD-SOI planar devices, RF switching |
Mechanical & Flat/Notch Standards (quick reference)
- 300 mm uses a single orientation notch; =200 mm often use primary/secondary flats.
- Bow/warp limits are specified per diameter and material; incoming QC measures TTV and warp before stock-in.
- Edge exclusion is defined on purchase order (typ. 2–3 mm) and affects usable die area.
Electrical Grade & Gettering
- Prime, Test, and Reclaim grades define metal/particle limits and surface quality.
- Intrinsic or lightly doped high-resistivity wafers for sensors/RF minimize substrate coupling.
- Epi layers can be engineered for gettering and defect reduction prior to FEOL.
Incoming Containers & Carriers
| Carrier |
Capacity |
Where Used |
Notes |
| Shipping Cassettes / Boxes |
13–25 wafers |
Vendor to fab receiving |
Cleanroom-packaged, shock-protected, vacuum-sealed options |
| SMIF Pods (150/200 mm) |
13–25 wafers |
Stockroom to tools in legacy/200 mm fabs |
Sealed mini-environment; reduces particle exposure |
| FOUP (300 mm) |
25 wafers |
AMHS/overhead transport to tools |
Front-Opening Unified Pod; fab automation standard |
| JLP / Panels (advanced fan-out) |
Panel format |
Advanced packaging lines |
Used for panel-level packaging (PLP) |
Typical Incoming QC (Dock-to-Stock)
- Visual inspection (scratches, chips, contamination)
- Flat/notch orientation and ID verification against PO
- Thickness, TTV, warp/bow metrology samples
- Particle level and metallic contamination audits (sampled)
- Epi thickness/uniformity (for epi wafers) via ellipsometry/reflectometry
Procurement Notes
- PO must specify diameter, material, orientation, resistivity/dopant, thickness, surface finish, epi (if any), edge exclusion, ID method, and container type.
- For compound wafers, include substrate dislocation density, epi layer structure, and bow/warp limits at temperature.
- For power devices (SiC, GaN), define micropipe/dislocation specs and epi doping/drift thickness.
