Wafer Doping

Doping introduces controlled amounts of impurity atoms — dopants — into specific regions of the silicon wafer to modify the local electrical conductivity. Pure silicon is a poor conductor; adding parts-per-million to parts-per-thousand of boron, phosphorus, arsenic, or antimony converts those silicon regions into p-type or n-type semiconductor material with precisely tuned carrier concentration. The transistor source and drain, the well regions, the threshold-voltage adjust layers, and numerous other electrical features of the device are defined by where dopants are placed and at what concentration.

Doping is a conditional step in the front-end loop, not a loop step. It runs selectively at transistor-formation stages — a handful of implant steps per layer, with more passes concentrated in the transistor tier and fewer in the BEOL stack. Doping pairs tightly with oxidation and annealing: oxidation often provides sacrificial or screening oxide for implant, and every implant is followed by an anneal that activates the dopants and repairs crystal damage. Equipment concentration is tight: ion implantation is effectively an Applied Materials–Axcelis duopoly, and rapid thermal annealing (RTA) systems concentrate at Applied Materials, Mattson Technology, and SCREEN.

Dopant Species

A small set of dopant elements covers essentially all silicon doping. The choice of dopant determines the conductivity type (p or n), the diffusion behavior during subsequent thermal steps, and the atomic-level interaction with the silicon lattice.

Doping Methods

Three methods introduce dopants into silicon. Ion implantation dominates modern CMOS by a wide margin; diffusion persists in specific applications; in-situ doping is used during epitaxy and some deposition steps.

Ion Implantation

Ion implantation is the workhorse doping method for modern semiconductor manufacturing. An implanter ionizes source material (BF₃, PH₃, AsH₃, B₂H₆ and others), separates the desired ion species in a magnetic mass analyzer, accelerates the ions to a selected energy, and steers the resulting beam across the wafer. Energy controls implant depth; dose (ion current × time) controls concentration. Modern implanters can deliver implant energies from a few hundred electron volts (for ultra-shallow junctions at advanced nodes) to several million electron volts (for deep wells and isolation implants).

Implanters divide into classes by energy range and dose capability. High-current implanters deliver heavy doses at low-to-moderate energies for source/drain and poly-gate doping. Medium-current implanters serve threshold-voltage adjust and lightly-doped drain applications. High-energy implanters reach MeV-range energies for retrograde well formation and deep buried layers. Plasma doping tools (PLAD) handle conformal ultra-shallow doping that conventional beam-line implantation struggles with at advanced 3D structures.

Implant Equipment Vendors

Ion implantation is effectively an Applied Materials–Axcelis duopoly. Applied Materials leads in the high-current and plasma-doping segments through the Varian Semiconductor implant product line (acquired by Applied in 2011). Axcelis is the independent implant specialist, with strong positions in high-energy and medium-current segments and a growing share at memory IDMs. Smaller vendors and legacy tool populations serve specialty and mature-node applications.

Annealing & Dopant Activation

Ion implantation deposits dopant atoms into the silicon lattice but leaves them sitting in interstitial positions that do not electrically activate, and it damages the crystal structure along the implant path. Annealing — a controlled thermal step — repairs the lattice damage and drives the dopant atoms into substitutional sites where they become electrically active carriers. Annealing must balance two competing requirements: enough thermal budget to fully activate dopants and repair damage, but not so much that the activated dopants diffuse out of the precise depth profile the implant created. At advanced nodes, where junction depths approach a few nanometers, this balance has pushed annealing toward shorter and shorter pulses.

Anneal Equipment Vendors

Rapid thermal processing (RTP) equipment concentrates at a handful of vendors, with substantial overlap between anneal tool suppliers and oxidation tool suppliers — the underlying lamp-based single-wafer thermal platform serves both applications.

Doping at Advanced Nodes

Doping has become significantly more complex as nodes have advanced. Three trends dominate. First, junction depths have shrunk to a few nanometers, requiring sub-keV implant energies and millisecond or laser annealing that were specialty processes a decade ago and are now mandatory at advanced logic. Second, three-dimensional transistor architectures (FinFET, GAA) have shifted demand toward conformal doping methods — plasma doping, in-situ doping during epitaxy — because beam-line ion implantation cannot uniformly dope the sidewalls of vertical fins or the surfaces of released nanosheets. Third, the material set has expanded beyond silicon: SiGe source/drain in advanced logic, silicon carbide power devices requiring high-energy implant at elevated wafer temperatures, and specialty III-V doping each have their own process requirements.

SiC power device doping is a particular specialty. SiC requires implants at wafer temperatures of 500 °C or higher (versus room temperature for silicon) because of the lower defect mobility in the SiC lattice, and requires anneals above 1600 °C with specialized capping to activate dopants. Axcelis holds a strong position in SiC implanters; specialty anneal equipment comes from vendors like Centrotherm. See SiC & GaN Power Modules for the device context.

Related Coverage

Parent: Front-End Fabrication

Peers in front-end: Wafer Cleaning · Oxidation · Deposition · Photolithography · Etching · CMP · Metallization · Metrology

Equipment & consumables: WFE Hub · Process Consumables · Process Gases

Cross-pillar dependencies: Process Nodes & Lines · SiC & GaN Power Modules · Bottleneck Atlas