System in Package (SiP)

Processor · memory · radios · sensors · passives · one package

A system in package puts a whole subsystem, processor, memory, radios, sensors, power management and dozens of passives, inside one shielded package; the Apple Watch S-series is the best-known example. Every die must be good before assembly: at 99% yield per die, a 10-die SiP works only about 90% of the time before a single assembly defect, so SiP makers test each die, each sub-assembly and the finished system.

Top view of a wearable-class system in package: application processor, stacked memory, power management, Wi-Fi and Bluetooth radio, RF front end with filters, sensors and dozens of passive components on one substrate under a metal shield. If each of 10 dies is 99% good, about 90% of assembled packages work before any assembly defect. ONE PACKAGE, ONE SUBSYSTEM (TOP VIEW, NOT TO SCALE) Processor LOGIC, ADVANCED NODE Memory, stacked LPDDR ON TOP PMIC POWER Radio WI-FI, BT RF front end PA, SWITCHES, FILTERS Sensors MEMS Secure element AND NFC PASSIVES DASHED LINE: METAL SHIELD AGAINST RF INTERFERENCE YIELD BY DIE COUNT 100% 80% 60% 1 10 20 30 99% 99.5% DIES IN THE PACKAGE 10 dies at 99%: 90%
Integration
Functional, not bandwidth
10 dies at 99%
~90% yield
Best-known
Apple Watch SiP
Leading assembler
ASE and USI
US assembler
Amkor
Hub
Packaging

What makes a SiP

SiP Integrates Functions; CoWoS Integrates Bandwidth

CoWoS, Foveros and SoIC join a few related compute dies at very high bandwidth. A SiP joins many different parts, logic, memory, RF, analog, power, MEMS sensors and passives, so the package does a job the board used to do.

What makes a package a SiP
AttributeDescriptionWhy it matters
Mixed diesDies from different nodes, materials and foundries in one packageEach function uses its best process: logic at an advanced node, PAs on GaAs, power on BCD, sensors on MEMS
Passives insideCapacitors, inductors, filters and crystals next to the diesFrees board area and shortens high-frequency paths
A whole functionThe package does a system or subsystem jobThe customer buys a module, not a chip; the board shrinks to power and connectors
Small and thinFootprint and profile far below the board-level equivalentMakes watches, earbuds and rings possible
Mixed interconnectWire bond, flip-chip and fan-out RDL in one packageEach component gets the connection it needs

Construction

Five Ways to Build a SiP

SiP is a design approach more than a single process, and one product often mixes methods; the Apple Watch SiP combines fan-out and laminate construction with stacked memory and heavy passive integration.

SiP construction approaches
ApproachConstructionTypical uses
Laminate SiPDies and passives on an organic laminate; wire-bonded or flip-chip; overmolded and shieldedRF front ends, car sensor modules, IoT radio modules
Fan-out SiPSeveral dies in a reconstituted wafer with RDL between themPhone and wearable modules; overlaps multi-die fan-out
Package on packageMemory package stacked on the logic packagePhone processors with LPDDR on top
3D SiPStacked dies with TSVs or hybrid bonds alongside other partsCompute and memory modules; emerging
Embedded-die SiPSome dies laminated inside the substrateUltra-thin car and medical modules

Known-good die

One Bad Die Scraps the Whole Package

Package yield is roughly the product of the yields of its dies: at 99% per die, 10 dies give about 90% and 20 dies about 82%, before any assembly defect. SiP makers answer with wafer-level test of every die, test after singulation, test of sub-assemblies, and system-level test of the finished package that runs the logic, memory, radios, sensors and power paths together. See Final Test and Advanced Packaging Test.

Applications

Where SiPs Go

SiP applications
ApplicationWhat is insideExamples
WearablesProcessor, memory, radios, sensors, power management and passivesApple Watch S-series SiP; earbuds and smart rings
RF front-end modulesPAs, switches, filters, LNAs and control5G and Wi-Fi front ends from Qualcomm, Skyworks, Qorvo, Broadcom and Murata; see RF Modules
Phone processor plus memoryProcessor with LPDDR stacked on topApple A-series on InFO-PoP; Qualcomm Snapdragon with LPDDR PoP
Car sensor modulesSensor die, analog front end and controller in an automotive-grade package77 GHz radar, ADAS camera and ultrasonic modules
IoT radio modulesMCU, radio, memory and power in one certified moduleNordic, Silicon Labs, Espressif and Murata modules
Medical devicesLow-power compute, sensor interface, radio and battery managementHearing aids, implants and wearable monitors

Who builds SiPs

SiP Assembly Runs at the OSATs

Fabless and system companies design the SiP and contract the assembly; Apple designs the Watch SiP, and Qualcomm, Skyworks and Qorvo design their RF modules. The assembly sits mostly in Taiwan, China and Southeast Asia; Amkor is the only US-headquartered SiP assembler at scale, and its plants are abroad.

SiP assemblers
CompanyHQPosition
ASE and USITaiwanLargest SiP assembler; USI (Universal Scientific Industrial) builds wearable and phone SiPs, including for Apple
AmkorUnited StatesVolume SiP for phones, RF and cars from Korea, the Philippines, Vietnam and other sites
JCETChinaSiP for Chinese phone makers and RF module vendors
Luxshare and GoertekChinaWearable and earbud SiPs inside device assembly
MurataJapanRF and connectivity modules built in-house
Powertech and specialty OSATsTaiwan and othersMemory-led and specialty SiP

Record

Page Record

Covers
SiP attributes, construction approaches, known-good-die test, applications and assemblers
Sources
ASE, USI, Amkor, JCET and Murata disclosures; yield arithmetic computed from per-die yield
Last verified
October 2026