Semiconductor Die Attach

Die attach is the step immediately after dicing. Each separated die — still sitting on the expanded dicing tape — is picked up by a bonder and placed onto its package carrier: a leadframe, an organic substrate, a silicon interposer, or the top of another die in a stacked assembly. A bonding medium secures the die and, in many cases, also carries heat from the die into the package body. The operation is fast (modern bonders place thousands of dies per hour) and the accuracy budget is tight (micrometers of placement error at the high end).

The concentration story at die attach is at the equipment layer and at the bonding-materials layer. Die bonders concentrate at ASMPT, BESI, and Kulicke & Soffa, with Palomar Technologies serving specialty optoelectronic and defense applications. Bonding materials split by chemistry: Henkel, Nagase ChemteX, and Shin-Etsu dominate epoxy adhesives; Indium Corporation and MacDermid Alpha (the former Alpha Assembly Solutions) supply solder preforms and sintering pastes; Hitachi Chemical (Resonac), Nitto Denko, Lintec, and Furukawa Electric supply die-attach films. The choice of bonding method is driven by the end application — a $2 MCU in a QFN package uses epoxy; a SiC traction inverter die uses silver sinter; a flip-chip CPU uses solder bumping (covered under Flip-Chip Bonding rather than here).

The Die Attach Flow

Die attach is a three-sub-step loop that repeats for every die placed. The loop runs continuously at the bonder: pick, place, cure (or set). Cure timing and bonder architecture differ across bonding mediums, and the throughput of the line is often gated by cure rather than by the pick-and-place operation itself.

The pick-and-place sub-steps happen at the bonder itself; cure is either on the bonder (for fast adhesives) or downstream in an oven, reflow tunnel, or sinter press (for bonding mediums with longer set times). Batch cure in an oven is standard for volume epoxy lines — many substrates carry through cure together — while high-performance solder and sinter processes run inline with tight thermal profile control.

Bonding Mediums

Four bonding mediums dominate die attach in volume production. Each sits at a different point on the cost, thermal-performance, and reliability curve, and each has its own materials supply chain and equipment tuning.

Epoxy is the volume default. Conductive silver-filled epoxy handles cases where a ground path through the die is needed; non-conductive epoxy is the lower-cost option for parts where the electrical path runs through wire bonds. Cure temperatures for most die-attach epoxies sit in the 150–200 °C range, and cure times at volume lines are typically ten to sixty minutes in a batch oven.

Eutectic solder attach delivers higher thermal conductivity at significantly higher material cost (gold-silicon solder is expensive) and higher process temperatures (gold-silicon eutectic melts near 363 °C). It is the default for high-reliability logic parts, RF power amplifiers, LEDs, and laser diodes where the thermal path from die to package is performance-critical.

Silver sintering has become the enabling die-attach technology for wide-bandgap power devices. SiC and GaN transistors run at junction temperatures above the melting point of conventional lead-free solders; silver sinter bondlines survive those temperatures without creep or fatigue. The bondline is typically formed at 200–250 °C under pressure in the 5–30 MPa range. Silver-sinter adoption has grown in lockstep with SiC traction inverter production for electric vehicles and with GaN power module production for data-center and industrial applications. See SiC & GaN for the device-side view.

Die-attach film (DAF) pre-applies the adhesive to the wafer back-side during dicing tape lamination — the wafer arrives at the bonder with each die already carrying its own adhesive layer. DAF is the standard for stacked-die memory packages and for thin-die applications where paste dispensing would introduce bondline thickness variation. DAF thickness is tightly controlled by film manufacture, which eliminates a major yield variable at the bonder.

Equipment Concentration

Die bonders are a duopoly-plus-one market. ASMPT leads by volume with the broadest product line; BESI specializes in the higher-performance tier (flip-chip, hybrid bonding precursors, high-accuracy placement); Kulicke & Soffa operates across both mass-market and advanced die attach with particular strength in high-accuracy platforms. Palomar Technologies and several smaller specialty vendors handle the niche tiers — optoelectronics, defense, MEMS — where extreme precision, unusual die form factors, or low-volume custom processes are the norm.

Bonder throughput is measured in units per hour (UPH), with high-volume mass-market bonders hitting 30,000+ UPH on simple geometries and advanced-packaging bonders running 1,000–5,000 UPH where placement accuracy of one micrometer or better is required. Throughput scales down as accuracy requirements tighten: hybrid bonding precursor steps (pre-flat die placement for hybrid bonders downstream) run at a fraction of mass-market throughput because the alignment tolerance is sub-micron.

Bonding Materials Supply

Die-attach materials are a specialty chemicals layer with geographic concentration in Japan, Germany, and the United States. The material itself is cheap in absolute terms relative to the die being bonded, but the qualification depth at any given assembly line makes supplier switching slow — once a material is qualified into an automotive or high-reliability program, requalification on an alternate supplier can take quarters to years.

Placement Accuracy & Bondline Quality

Two operational variables govern die-attach quality: placement accuracy and bondline integrity. Placement accuracy — the positional error between the intended die location and the actual placed location — ranges from tens of micrometers on low-cost mass-market bonders to sub-micron on advanced-packaging platforms. The tolerance requirement comes from the downstream interconnect step: wire bonding tolerates relatively loose die placement because the wire bonder aligns to the die's bond pads at the moment of each wire; flip-chip requires much tighter placement because the solder bumps must land on substrate pads without shorts to adjacent pads.

Bondline integrity covers thickness uniformity, voiding, and tilt. A bondline with voids does not conduct heat uniformly and introduces stress concentrations under thermal cycling. A tilted die introduces height variation across its surface, which can fail wire-bond loop height targets or flip-chip bump engagement uniformity. Bondline thickness targets range from a few micrometers for thin DAF applications to 50 µm or more for silver sinter under power dies. X-ray inspection and acoustic microscopy are the standard post-attach metrology techniques to detect voids and bondline defects before the package moves to interconnect.

Cure, Reflow, Sinter Equipment

The thermal set step that follows pick-and-place uses different equipment by bonding medium. Epoxy cure runs in batch ovens or conveyor ovens at 150–200 °C with residence times of tens of minutes to hours — the bottleneck at high-volume epoxy lines is often oven throughput rather than bonder speed. Solder reflow uses conveyor reflow ovens with controlled atmosphere (nitrogen or forming gas) and precise thermal profiles to melt the solder, achieve wetting, and cool without thermal shock. Silver sinter uses a dedicated sinter press that applies heat and mechanical pressure simultaneously — sinter presses are specialty equipment from a smaller vendor base (Boschman, ASMPT, PINK) and qualification is tight for automotive power device use.

For SiP and MCM assemblies where multiple dies attach to a common substrate, the attach sequence may alternate with reflow or cure steps to build the substrate in a staged process — higher-temperature bonds placed first, lower-temperature bonds later, so that each subsequent thermal step does not reflow or disturb prior bonds. This hierarchical thermal design is a quiet engineering discipline inside advanced packaging.

Yield & Cost

Die-attach yield at a mature line runs above 99%. Yield loss is concentrated at pickup (cracked die, tape residue), placement (misalignment at fine geometries), and cure (voids, warpage). Cost per die is a few cents to low-tens-of-cents at volume epoxy lines and rises significantly at solder, sinter, and DAF operations due to material cost and slower throughput. For high-ASP die attach operations — SiC power modules, AI accelerator precursors, HBM stack bonding — the attach step is a small fraction of total package cost but a disproportionately large share of yield risk because scrap at attach wastes an expensive die.

Market Outlook

Die-attach equipment demand has two growth vectors that run ahead of baseline semiconductor unit growth: silver sintering for SiC and GaN power devices, and high-accuracy advanced-packaging bonders for chiplet assemblies, HBM stacking, and AI accelerator integration. Baseline epoxy and wire-bonded attach for MCUs, analog, and mature logic tracks overall semiconductor unit volume. The biggest long-duration concentration risk is the high-accuracy advanced-packaging bonder layer, where BESI and Kulicke & Soffa lead the narrow tool supply that enables hybrid bonding preparation and chiplet integration — a tool supply that intersects directly with the advanced-packaging bottleneck narrative.

Related Coverage

Parent: Back-End Assembly

Peers in back-end assembly: Wafer Dicing · Bonding Overview · Encapsulation · Final Test

Downstream interconnect: Wire Bonding · Flip-Chip Bonding

Advanced-packaging bonding: Advanced Interconnects (Hybrid Bonding)

Equipment & consumables supply: Fab Equipment · Fab Consumables

Cross-pillar dependencies: SiC & GaN (silver-sinter-enabled power devices) · HBM (stacked-die attach) · Bottleneck Atlas