Flip-Chip Bonding

C4, copper pillar and micro-bumps · thermocompression bonding · underfill and FCBGA substrates

Every CPU, GPU and AI accelerator is flip-chip bonded, and each drop in bump pitch multiplies the connections a die can carry. At HBM and CoWoS pitches the bonder now forms every joint itself, and HBM's TC bonders come mainly from four makers: Hanmi, ASMPT, SEMES and Hanwha. Below 10 µm the work passes to hybrid bonding.

Connections per square millimeter by interconnect pitch, computed for a square grid: C4 solder bumps at 150 micrometers, about 44; copper pillars at 40 micrometers, about 625; micro-bumps at 25 micrometers, about 1,600; hybrid bonds at 9 micrometers, about 12,300. HBM stacks are built today with thermocompression bonders from Hanmi, ASMPT, SEMES and Hanwha; hybrid bonding is next. CONNECTIONS PER mm², SQUARE GRID (COMPUTED) 1 10 100 1,000 10,000 100,000 C4 solder bump 150 µm PITCH 44 Copper pillar 40 µm PITCH 625 Micro-bump 25 µm PITCH 1,600 Hybrid bond 9 µm PITCH ~12,300 LOG SCALE. SOLDER ENDS NEAR 10 µm; BELOW IT, COPPER BONDS DIRECTLY TO COPPER. WHO BUILDS HBM STACKS, AND WITH WHAT SK hynix MR-MUF HANMI, ASMPT Samsung TC-NCF SEMES (IN-HOUSE) Micron TC-NCF HANMI, ASMPT, BESI ON TEST BONDER SPLITS: TRENDFORCE AND KOREAN TRADE PRESS, 2025-2026 (REPORTED).
Copper pillar pitch
40-100 µm
Micro-bump pitch
25-55 µm
TC bonder market
~$759M (2025)
Plan, 2028
~$1.6B
US merchant flip-chip
From 2028
Hub
Process

The flip-chip flow

Bump the Wafer, Then Flip the Die

Flip-chip connects a die through an array of bumps across its face, giving thousands of short connections where wire bonding gives hundreds of long ones.

Flip-chip turns the die face down and joins it to the substrate through bumps spread across its whole surface instead of wires around its edge. It is two operations in two places: wafer bumping, done on the whole wafer at a foundry or advanced OSAT, and flip-chip attach, done die by die on the assembly floor.

Flip-chip attach in four steps: the bumped die is picked from the dicing tape and flipped face down; it is placed on the fluxed substrate pads; reflow melts the solder and forms the joints; underfill epoxy is dispensed at the die edge, wicks under the die and is cured. 1. Pick and flip SUBSTRATE FACE DOWN 2. Place SUBSTRATE 3. Reflow SUBSTRATE ~250 °C, NITROGEN 4. Underfill SUBSTRATE EPOXY WICKS UNDER DIE FINE-PITCH PARTS REPLACE STEP 3 WITH A THERMOCOMPRESSION BOND: HEAT AND FORCE THROUGH THE DIE, ONE DIE AT A TIME.
Flip-chip attach steps
StepWhat happensMain yield risk
Pick and flipBumped die lifted from the dicing tape and turned face down; vision aligns it to the substrateBump damage, tilt, misalignment at fine pitch
PlaceDie set on fluxed substrate pads to within a few micrometers, under 1 µm for fine-pitch pillarsOffset beyond the bump-to-pad overlap, bridging
ReflowSolder melts and wets the pads in a nitrogen oven, then freezesVoids, non-wet bumps at warped corners, head-in-pillow joints
UnderfillEpoxy dispensed at the die edge wicks under the die by capillary action and is curedVoids under the die, delamination, poor fillet

Underfill is structural, not optional. Silicon expands about 3 ppm per degree and an organic substrate about 15 to 17, so every power cycle tries to shear the joints. Underfill glues die to substrate and spreads that strain over the whole die, extending joint life by one to two orders of magnitude.

Bump types

Each Pitch Step Multiplies the Connections

Four interconnect shapes drawn at relative pitch. A C4 solder ball at 150 micrometers; a copper pillar with a solder cap at 40 to 100 micrometers; a micro-bump at 25 to 55 micrometers; and a hybrid bond, copper pad to copper pad with no solder, below 10 micrometers. C4 bump 100-200 ΜM PITCH SOLDER BALL COLLAPSES Copper pillar 40-100 ΜM PITCH PILLAR HOLDS ITS HEIGHT Micro-bump 25-55 ΜM PITCH UNDERFILL BETWEEN BUMPS Hybrid bond UNDER 10 ΜM PITCH COPPER TO COPPER, NO SOLDER DIE IN BLUE, COPPER IN COPPER, SOLDER IN GRAY, SUBSTRATE OR LOWER DIE BELOW. RELATIVE, NOT TO SCALE.
Bump architectures
InterconnectPitchWhere it is used
C4 solder bump (lead-free SnAgCu)100 to 200 µmOlder server CPUs, FPGAs, networking chips, mid-range FCBGA
Copper pillar with solder cap40 to 100 µm, below 40 µm at the leading edgeCurrent CPUs, GPUs, AI accelerators and flagship mobile SoCs
Micro-bump25 to 55 µmDie to interposer and die to die in 2.5D and 3D: CoWoS, EMIB, HBM stacks
Hybrid bondUnder 10 µm, 9 µm in productionCopper to copper with no solder: AMD 3D V-Cache on TSMC SoIC; see Advanced Die Interconnects

Copper pillar replaced the C4 ball on most advanced chips because the pillar keeps its height while only the small solder cap melts, so bumps can sit closer without bridging and carry more current. Each step down in pitch multiplies the connections per square millimeter: a square grid at 150 µm holds about 44, at 40 µm about 625, and at 9 µm about 12,300.

Wafer bumping

Bumping Is a Front-End Process

Bumps are built on the whole wafer before it is diced. For copper pillar, the sequence is a titanium and copper seed layer (the under-bump metallization), a thick resist patterned with openings over each pad, electroplated copper, a plated solder cap, resist strip and seed etch. That is lithography, plating and etch, which is why bumping sits at foundries and the largest OSATs, not on ordinary assembly lines.

Wafer bumping
Who bumpsTools
TSMC and Samsung for their own advanced-node wafers; ASE, Amkor, JCET and SPIL for merchant work; Intel in housePlating: Lam Research (SABRE 3D), Applied Materials, ACM Research; seed deposition: Applied; coat, develop and strip: Tokyo Electron; ball mount: ASMPT

Bonders

At Fine Pitch the Bonder Makes the Joint

For most flip-chip parts, the bonder only places the die and an oven forms the joints. At the finest pitches and on stacked dies, the bonder does the joining itself: a thermocompression (TC) bonder heats and presses each die for a few seconds, so every bump forms at once on a flat, controlled stack. TC bonders are slower and costlier, and they are the tool behind every HBM stack and most CoWoS modules. ASMPT puts the TC bonder market at about $759 million in 2025 and $1.6 billion in 2028.

Flip-chip and TC bonder makers
MakerBasePosition
Hanmi SemiconductorIncheon, KoreaLong the main TC bonder supplier to SK hynix and Micron; building a hybrid bonder plant in Incheon for the second half of 2026
ASMPTSingaporeReported to supply about half of SK hynix's HBM4 TC bonders, from near zero HBM share in 2024; flux and fluxless TC tools
SEMESCheonan, KoreaSamsung's in-house equipment arm; supplies most of Samsung's HBM bonders
Hanwha SemitechChangwon, KoreaTC bonders and early hybrid bonders developed with SK hynix
BESIDuiven, NetherlandsHigh-accuracy flip-chip and TC bonders; partner with Applied Materials on the Kinex hybrid bonder; Applied owns about 9%
Kulicke & SoffaSingapore and Fort Washington, PAFlip-chip and fluxless TC bonders for logic
Toray Engineering, Shibaura, ShinkawaJapanTC and flip-chip bonders for Japanese and Asian lines

Below about 10 µm, solder stops working and hybrid bonding takes over. Korean analysts expect hybrid bonding to carry about half of HBM production by 2028, and Hanmi says HBM4 and HBM5 can still be built on TC bonders. The move from bonder to hybrid bonder shifts the work from back-end assembly into a cleanroom with front-end polish and plasma steps.

HBM stacking

HBM Is Flip-Chip Bonding 16 Times Over

An HBM stack is flip-chip bonding repeated 12 to 16 times: each DRAM die, thinned to about 30 µm for 16-high HBM4, is bonded face down on the one below through micro-bumps and through-silicon vias. Two methods are in volume:

  • MR-MUF (mass reflow, molded underfill): SK hynix tacks all dies in place, reflows the stack at once and fills the gaps with a molded underfill from Namics. It plans to keep MR-MUF for 12- and 16-high HBM4 and HBM4E after testing fluxless bonding in late 2025. China's CXMT plans HBM with the same method in 2026.
  • TC-NCF (thermocompression with non-conductive film): Samsung and Micron laminate a film on each die and bond die by die on TC bonders.

The memory side is on HBM and Memory Modules.

Underfill and substrate

The Substrate Sets Cost and Yield

Flip-chip materials
MaterialWhat it doesMain suppliers
Underfill epoxyCapillary, no-flow or molded underfill loaded with silica to match expansionNamics, Henkel, Resonac, Nagase ChemteX, Shin-Etsu
Solder and fluxSnAgCu bump and cap alloys, low-alpha grades for memory; flux that strips oxide during reflowSenju Metal, Indium Corporation, MacDermid Alpha, Heraeus
FCBGA substrateMulti-layer laminate that fans fine bumps out to coarse board ballsIbiden, Unimicron, Nan Ya PCB, Shinko, AT&S, Samsung Electro-Mechanics; Shennan Circuits in China
ABF build-up filmDielectric layers inside nearly every high-pin-count substrateAjinomoto, with above 95% share

The substrate is the largest material cost in a high-end flip-chip package and the slowest to add capacity. Its warpage is also the main yield enemy at fine pitch: a bowed substrate leaves corner bumps unwetted, which is one reason AI modules moved to TC bonding. Substrate detail is on Substrates and Interposers.

Where it runs

Advanced Flip-Chip Arrives in the US in 2028

  • Made in US
  • US planned
  • Made abroad
Flip-chip and bumping sites
SiteLocationDoesStatusUS status
TSMC advanced packagingTaiwan (AP5 to AP8)Wafer bumping, CoWoS and SoIC for TSMC wafersOperatingMade abroad
ASE and SPILKaohsiung and Taichung, TaiwanBumping and flip-chip attach; CoWoS substrate stageOperatingMade abroad
Amkor K5Songdo, KoreaBumping and flip-chip for mobile and AI partsOperatingMade abroad
SK hynixIcheon and Cheongju, KoreaHBM stacking (MR-MUF)OperatingMade abroad
Intel Fab 9Rio Rancho, NMFoveros 3D stacking and flip-chip for Intel productsOperatingMade in US
Amkor PeoriaPeoria, AZBumping, flip-chip and CoWoS-class packagingProduction planned early 2028US planned
SK hynix West LafayetteWest Lafayette, INHBM stacking and packagingUnder construction; production planned 2028US planned
TSMC Arizona advanced packagingPhoenix, AZBumping, CoWoS and SoICPlanned; online before 2029US planned
Placeholder: other flip-chip and bumping rows from the fab dataset

Intel is the only company doing advanced flip-chip and die stacking in volume in the United States today, for its own products. Merchant flip-chip for AI accelerators arrives with Amkor Peoria and TSMC Arizona; until then, wafers from TSMC Fab 21 in Phoenix are bumped and packaged in Taiwan. Each chip's full supplier path is on the chip supplier rings.

Record

Page Record

Covers
Flip-chip attach flow, bump types, wafer bumping, TC and flip-chip bonders, HBM stacking, materials and sites
Sources
TrendForce (hybrid bonder market, October 2025; SK hynix MR-MUF and ASMPT orders, January 2026); The Tech Fund citing The Elec, JP Morgan and ASMPT (TC bonder shares and market size, March 2026); Digitimes (CXMT HBM, November 2025); Crypto Briefing on Applied Materials and BESI (October 2026); connections per mm² computed for a square grid
Last verified
October 2026