Advanced Die Interconnects

Through-silicon vias · micro-bumps · hybrid bonding

Connection density rises with the inverse square of pitch, so each step down the bond pitch multiplies the wires between two dies. Solder micro-bumps stop near 25 µm; hybrid bonding runs at 9 µm in Intel Foveros Direct and 6 µm in TSMC SoIC, about 28,000 connections per square millimeter, on tools from a handful of makers led by Besi with Applied Materials.

Connections per square millimeter rise with the inverse square of pitch: about 44 for 150 µm C4 bumps, 625 for 40 µm micro-bumps, 12,300 for Intel Foveros Direct at 9 µm, 27,800 for TSMC SoIC at 6 µm, and about 111,000 at the planned 3 µm, on a log scale. CONNECTIONS PER MM², BY BOND PITCH (LOG SCALE) 10 100 1,000 10,000 100,000 C4 flip-chip bumps DIE TO SUBSTRATE 44 at 150 µm Micro-bumps 2.5D DIE TO INTERPOSER, HBM4 625 at 40 µm Finest micro-bumps PRACTICAL SOLDER LIMIT 1,600 at 25 µm Foveros Direct INTEL CLEARWATER FOREST 12,346 at 9 µm TSMC SoIC AMD 3D V-CACHE, MI300 27,778 at 6 µm TSMC SoIC roadmap TARGETED BY 2029 49,383 at 4.5 µm Foveros Direct next SECOND GENERATION 111,111 at 3 µm Solder joints Hybrid bonds Roadmap
Micro-bump pitch
25-55 µm
SoIC pitch
6 µm
Foveros Direct
9 µm
SoIC density
~28,000/mm²
Hybrid bond leader
Besi + Applied
Hub
Packaging

Three technologies

TSVs, Micro-Bumps and Hybrid Bonds

Three technologies join dies inside 2.5D and 3D packages, and one module usually uses all three.

  • Through silicon
  • Solder joint
  • Direct bond
Die-to-die interconnects
TechnologyWhat it doesTypical pitch
Through-silicon vias (TSVs)Copper channels through thinned silicon, carrying signals and power from one face to the other5 to 50 µm
Micro-bumpsCopper pillars with solder caps joining a die to an interposer or another die25 to 55 µm
Hybrid bondingCopper pads fuse metal to metal while the oxide around them bonds; no solder9 µm and 6 µm in production; 3 µm planned

A 2.5D AI accelerator uses TSVs through the interposer, micro-bumps between the dies and the interposer, and C4 bumps and solder balls below. Wire bonding and flip-chip, which join one die to its package, are on Wire Bonding and Flip-Chip Bonding.

TSVs

Through-Silicon Vias

A TSV is a hole etched through thinned silicon, lined with dielectric and filled with copper. The foundry makes it in five steps:

  • Etch: deep reactive ion etching (DRIE) by the Bosch process cuts the via.
  • Liner: silicon oxide or nitride insulates the wall.
  • Seed: a thin copper layer is deposited for plating.
  • Fill: copper electroplating fills the via.
  • Planarize: chemical-mechanical polishing (CMP) flattens the surface; the wafer is later thinned to expose the via ends.

The tools come from the large wafer fab equipment makers, Applied Materials, Lam Research and Tokyo Electron. HBM stacks carry thousands of TSVs per die, and the stress they put on nearby transistors has shaped process work at SK hynix, Samsung and Micron.

Micro-bumps

Micro-Bumps Still Carry 2.5D and HBM4

A micro-bump joint is a copper pillar with a solder cap between two dies, with underfill around it; a hybrid bond joins recessed copper pads directly while the oxide around them bonds first, leaving no solder and no gap. Micro-bump joint 25 TO 55 µm PITCH, SOLDER AND UNDERFILL UPPER DIE LOWER DIE OR INTERPOSER COPPER PILLAR, SOLDER CAP, UNDERFILL BETWEEN Hybrid bond UNDER 10 µm PITCH, COPPER TO COPPER UPPER DIE LOWER DIE OR WAFER OXIDE BONDS FIRST; COPPER PADS FUSE IN ANNEAL BOND INTERFACE

Micro-bumps scale down the controlled collapse chip connection (C4) bumps of flip-chip bonding from about 150 µm to 25 to 55 µm pitch. They join dies to the interposer in CoWoS, EMIB and I-Cube, and they join the DRAM dies inside HBM4: SK hynix with mass-reflow molded underfill (MR-MUF), Samsung and Micron with thermocompression and non-conductive film (TC-NCF). Below about 25 µm the solder volume is too small for a reliable joint, which is where hybrid bonding takes over.

Hybrid bonding

Hybrid Bonding Removes the Solder

Hybrid bonding joins two die surfaces into one interface: the oxide bonds at room temperature, then an anneal grows copper grains across the pads.

  • Pitch: about an order of magnitude finer than micro-bumps.
  • Heat: no solder joint and no underfill in the heat path; Samsung reports more than 20% lower thermal resistance against thermocompression stacks.
  • Electrical: lower resistance, inductance and capacitance per connection.

It demands angstrom-level flatness, copper pads recessed a few nanometers below the oxide, front-end cleanliness and sub-micron alignment.

Wafer and die bonding

Wafer-to-Wafer and Die-to-Wafer

Two ways to hybrid bond
VariantProcessMain use
Wafer-to-wafer (W2W)Two finished wafers bonded face to face in one stepImage sensors (Sony, Samsung, OmniVision); YMTC Xtacking NAND; matched die sizes
Die-to-wafer (D2W)Tested dies placed one at a time onto a target waferTSMC SoIC, Intel Foveros Direct, future HBM; mixed die sizes and nodes

W2W is fast but needs matching dies on both wafers and cannot screen out bad dies. D2W places only known-good dies, at hundreds to about 2,000 placements an hour.

Bonding tools

Bonding Tool Suppliers

Bonder makers
CompanyHQPosition
Besi (BE Semiconductor Industries)NetherlandsHybrid bonding leader; Kinex die-to-wafer system with Applied Materials (about 1,600 placements an hour); tools at TSMC, Intel, Samsung and SK hynix; about 50 tools reportedly ordered for Samsung Pyeongtaek
Applied MaterialsUnited StatesBesi partner and shareholder; supplies the CMP, deposition and clean steps hybrid bonding depends on
Tokyo ElectronJapanWafer-to-wafer and die-to-wafer bonding platforms
EV GroupAustriaWafer bonding including hybrid; strong in image sensor wafer-to-wafer; partners with ASMPT
SUSS MicroTecGermanyWafer bonding and lithography for advanced packaging
Hanwha SemitechSouth KoreaHybrid bonders with SK hynix since 2021; SHB2 Nano second generation
Hanmi SemiconductorSouth KoreaLeading thermocompression (TC) bonder for HBM; hybrid bonder plant in Incheon from 2H 2026, HBM6 bonder planned by end of 2027
ASMPTSingaporeTC bonders and hybrid bonding systems for HBM
NauraChinaQomola HPD30 die-to-wafer hybrid bonder, shown at SEMICON China in March 2026; customer process verification done

Analysts put Besi's hybrid bonding revenue near €476 million in 2026, up from about €36 million in 2023. A hybrid bonder costs more than twice a TC bonder, and a new vendor needs quarters of qualification before it enters a TSMC SoIC or HBM line.

Surface preparation

Surface Preparation Decides Bond Yield

  • CMP: planarizes the surface and sets the copper pad recess; slurry and pad choice decide yield. See Planarization (CMP).
  • Plasma activation: prepares the oxide to bond.
  • Clean: removes copper oxide, particles and organics.
  • Handling: some hybrid bonding steps run in ISO 3 to ISO 4 cleanrooms, against ISO 6 for conventional assembly.

Programs

Where Hybrid Bonding Runs Today

  • In production: TSMC SoIC (AMD 3D V-Cache, MI300, Fujitsu Monaka), Intel Foveros Direct (Clearwater Forest), stacked image sensors and YMTC Xtacking NAND.
  • Next: HBM4E or HBM5 stacks; Samsung targets hybrid-bonded HBM volume in 2029 to 2030, and SK hynix is validating 12-high hybrid-bonded samples.
  • Later: the HBM-to-interposer joint in 2.5D, if its pitch falls below about 25 µm.

Architectures are on 3D IC Packaging.

Outlook

Interconnect Outlook

TSVs stay in every 2.5D and 3D design. Micro-bumps stay at the 2.5D die-to-interposer joint and inside HBM through HBM4. Hybrid bonding spreads from logic stacking to memory as pitch falls; TSMC targets 4.5 µm by 2029 and Intel 3 µm in its next Foveros Direct. Hybrid bonder output from Besi, Tokyo Electron, Hanwha Semitech, Hanmi and Naura sets how fast that happens.

Record

Page Record

Covers
TSVs, micro-bumps and hybrid bonding: pitch, density, process, tool suppliers and production programs
Sources
Tom's Hardware (hybrid bonding roadmap, September 2026), TrendForce (bonder market, SEMICON China 2026), company releases (Besi, Applied Materials, Hanmi, Hanwha, Naura, TSMC, Intel)
Last verified
October 2026