Die Advanced Interconnects

Advanced interconnects are the die-to-die connection technologies that enable 2.5D and 3D integration. Three technologies cover the full range: through-silicon vias (TSVs) provide the vertical pathways through thinned silicon for stacked dies and silicon interposers; micro-bumps are the fine-pitch solder connections that join dies to interposers or to each other in early-generation 3D stacks; hybrid bonding is the direct copper-to-copper metallic bond at sub-10 µm pitch that is replacing micro-bumps in next-generation advanced packaging. The evolution is directional: TSVs and micro-bumps remain in production at scale, but the die-to-die connection method is moving from micro-bumps to hybrid bonding wherever pitch and performance requirements justify it.

Hybrid bonding is the active frontier and the content this page is primarily about. It is the enabling technology for HBM4 (the first HBM generation using hybrid bonding at the die-to-die interface), TSMC SoIC (3D die-on-die stacking), Intel Foveros Direct (3D compute tile stacking without micro-bumps), and the next generation of AI accelerator architectures that stack compute logic vertically. Hybrid bonding equipment is one of the tightest concentration points in all of advanced packaging: BESI (in partnership with Applied Materials) is the commercial leader with the majority of the installed base, and Tokyo Electron is the primary alternative supplier. The global installed base is small and every new advanced packaging program requiring hybrid bonding competes for the same limited tool supply.

This page sits on the advanced-packaging side of the back-end pillar. Traditional die bonding (wire bonding and flip-chip) is covered at Bonding Overview under Back-End Assembly. The two lineages are structurally different: traditional bonding uses wires or solder bumps to connect a single die to a package; advanced interconnects connect multiple dies to each other at much higher density using TSVs, micro-bumps, and hybrid bonding.

The Three Technologies

The three technologies are not competitors at a single interface — they work together inside a module. A typical 2.5D AI accelerator uses TSVs through the silicon interposer (vertical paths from HBM and logic dies down to the substrate), micro-bumps between the dies and the interposer top surface, and BGA balls between the interposer's substrate underneath and the board. A typical next-generation 3D module adds hybrid bonding at the die-to-die interface where micro-bumps would have been used in the prior generation. The migration from micro-bumps to hybrid bonding at the die-to-die interface is the active architectural transition.

Through-Silicon Vias (TSVs)

TSVs are the vertical plumbing that makes silicon interposers and TSV-stacked dies possible. A TSV is a cylindrical hole etched through a thinned silicon wafer, lined with an insulating dielectric, and filled with copper. The resulting copper-filled via provides an electrical connection from one face of the silicon to the other. Without TSVs, a silicon interposer would have only surface routing, and stacked dies would have no vertical electrical path except around their edges.

TSV fabrication is a multi-step process performed at the foundry: deep silicon etch (using Bosch-process DRIE plasma etch), dielectric liner deposition (silicon oxide, silicon nitride), copper seed deposition, copper electroplating to fill the via, CMP to planarize the top surface. For interposers, the TSVs are patterned in a silicon wafer that is then back-end routed, thinned to expose the via backsides, and mounted to the assembly. For TSV-stacked dies (HBM, some 3D logic), the TSVs are fabricated in the device wafer itself during or after front-end fabrication. TSV equipment concentrates at the same major WFE vendors (Applied Materials, Lam Research, Tokyo Electron) rather than at specialty packaging equipment vendors.

TSV pitch and density continue to tighten. Early-generation TSVs at 50 µm pitch with 25 µm diameters have given way to more aggressive geometries, and current-generation HBM stacks use TSV patterns that are dense enough to constrain thermal design and mechanical stress management. TSV-induced stress on adjacent transistor layers is a front-end-packaging co-design concern that has shaped TSMC, Samsung, and SK hynix process development.

Micro-Bumps

Micro-bumps are the fine-pitch solder bumps that join a die face to another surface — another die, an interposer, or a package substrate — in 2.5D and early 3D architectures. They are structurally similar to flip-chip bumps (see Flip-Chip Bonding) but much smaller, typically 25–55 µm pitch versus the 100 µm and larger pitch of traditional flip-chip C4. Micro-bump construction is essentially a fine-pitch flip-chip process: copper pillar with solder cap, plated on under-bump metallization at the foundry, reflowed to make the joint at the advanced packaging line.

Micro-bumps are the *current* state of the art for 2.5D die-to-interposer connection in CoWoS, I-Cube, and EMIB architectures. They are also the *previous* state of the art at the die-to-die interface in HBM3 and HBM3E stacks, in original-generation Foveros, and in early TSMC 3D integration — positions where hybrid bonding is replacing them in next-generation products. Micro-bump pitch reduction has a practical floor determined by solder volume physics: at pitches below ~25 µm, the solder volume becomes too small to form reliable joints, which is the reason the industry is transitioning to hybrid bonding for finer-pitch applications rather than continuing to shrink micro-bumps.

Hybrid Bonding: The Frontier

Hybrid bonding is the copper-to-copper direct metallic bond at sub-10 µm pitch with no solder bumps. The name reflects the technology's hybrid nature: copper pads bond metal-to-metal at the pad locations, while the surrounding dielectric bonds oxide-to-oxide between the two surfaces. The result is a single, continuous bonded interface with no gap, no solder, no underfill, and no intermediate layers.

The physical advantages over micro-bump bonding are substantial. Pitch can scale below 10 µm and, in advanced programs, approach 1 µm — an order of magnitude finer than micro-bumps. With no solder, there is no thermal resistance at the joint interface, which dramatically improves heat extraction through the stack. There is no underfill because no gap exists between the two bonded surfaces. Interconnect parasitics (resistance, inductance, capacitance) drop substantially at the finer pitch, enabling higher signal speeds and lower power per interconnect.

The physical requirements are equally substantial. Both bonded surfaces must be prepared to atomic-level flatness — surface roughness in the angstrom range. The copper pads must be slightly recessed into the dielectric so that dielectric-to-dielectric contact happens first and copper-to-copper contact completes as the copper expands during the bond anneal. Surface contamination (organics, particles, native oxides) must be controlled at levels that challenge even advanced cleanroom practices. Alignment accuracy at sub-micron level is required to ensure copper pads overlap correctly at sub-10 µm pitch. The bonding process itself uses room-temperature pad-to-pad contact followed by a thermal anneal that forms the metallic bond through copper grain growth across the interface.

Wafer-to-Wafer vs. Die-to-Wafer

Hybrid bonding comes in two process variants with different economics and different applications.

W2W bonding throughput is very high — an entire pair of wafers bonds in one cycle — but is economically viable only when the two wafers carry dies of the same dimensions, aligned at the wafer level. This is common in CMOS image sensors, where the sensor pixel array and the image signal processor are fabricated on separate wafers and bonded face-to-face; it is also being applied in specialized memory-on-memory applications.

D2W bonding is the variant that matters most for chiplet-based advanced packaging. AI accelerators, server CPUs, and advanced SoCs use dies of different sizes, from different process nodes, and often from different foundries; bonding them at the wafer level is geometrically impossible. D2W handles the heterogeneous case by placing dies one at a time onto a target wafer with sub-micron accuracy. Throughput is much lower than W2W — hundreds of dies per hour rather than thousands per hour — and each die requires sub-micron placement, making the bonder specification extremely demanding. D2W is the variant BESI and Applied Materials have co-developed for the AI accelerator and chiplet market.

Equipment Concentration

Hybrid bonding equipment is one of the tightest concentration points in semiconductor manufacturing outside of EUV lithography. Three vendors hold essentially all of the commercial installed base.

The concentration reflects the extreme technical demands of hybrid bonding tool development. Surface preparation, alignment optics, thermal control, contamination management, and throughput optimization have to be co-engineered; the knowledge is built up over years of joint process development with foundry and IDM partners. New entrants into hybrid bonding face both a technology gap and a qualification gap — even if a new tool were technically capable, qualifying it into a TSMC SoIC line or an SK hynix HBM4 line would take quarters of process development. This is why the concentration is expected to remain tight through the end of this decade.

Surface Preparation

The enabling discipline underneath hybrid bonding is surface preparation. A hybrid bond cannot form reliably unless the copper pads on both surfaces are free of oxide, the dielectric surfaces around them are at angstrom-level flatness, and the entire surface is free of particle and organic contamination at densities approaching front-end fab standards. The preparation sequence typically includes CMP (chemical-mechanical polish) to planarize the bonding surface, plasma treatment to activate the dielectric, chemical clean to remove copper oxides, and tightly controlled handling to preserve the prepared state.

CMP for hybrid bonding is a specialized variant of the CMP used in front-end interconnect formation; see Planarization (CMP) for the front-end context. The hybrid bonding variant has tighter flatness requirements — the copper pads must be recessed below the dielectric surface by precisely a few nanometers so that dielectric contact forms first during bonding and copper contact completes during thermal anneal. CMP slurry formulation, pad selection, and process control become determining factors in hybrid bond yield.

The cleanroom environment for hybrid bonding is more demanding than traditional advanced packaging — some hybrid bonding operations run at Class 10 or Class 1 levels, comparable to front-end lithography cleanrooms rather than Class 1000 assembly cleanrooms. The technology has effectively moved parts of the back-end into front-end cleanliness regimes.

Applications & Production Programs

Hybrid bonding is in production at several flagship advanced packaging programs and expanding into next-generation architectures.

CMOS image sensors are the longest-running volume application of hybrid bonding and the reason wafer-level hybrid bonding equipment exists as commercially mature. The transfer of that know-how into die-to-wafer bonding for chiplets and HBM has been the critical enabler of the current advanced packaging generation.

The Future of the Die-to-Die Interface

The trajectory is clear: the die-to-die interconnect layer is migrating from micro-bumps to hybrid bonding wherever pitch and performance requirements justify the higher complexity. HBM4 is the first mainstream HBM generation using hybrid bonding. TSMC SoIC, Intel Foveros Direct, and Samsung's equivalent 3D programs are all using hybrid bonding for die-on-die stacking. The next generation of AI accelerators is expected to use hybrid bonding broadly at chiplet-to-chiplet interfaces.

Micro-bumps will persist at the die-to-interposer interface in 2.5D architectures for as long as 2.5D remains the dominant AI accelerator form factor — the pitch requirement at that interface is currently in the 40–55 µm range, which micro-bumps can handle economically. If future 2.5D architectures push die-to-interposer pitch below 25 µm, hybrid bonding will migrate into that layer as well. TSVs will continue to evolve alongside both interface technologies, since vertical pathways through silicon are architecturally required for 2.5D and 3D integration regardless of the in-plane interconnect method.

The equipment concentration story is expected to intensify. Hybrid bonding equipment capacity is the gating constraint on how fast HBM4 ramps, how fast TSMC SoIC expands, how fast Intel scales Foveros Direct — and the tool supply comes from a three-vendor base that cannot add capacity on quarters-scale timelines. This is a binding constraint comparable to CoWoS capacity in its strategic significance through the remainder of this decade.

Related Coverage

Parent: Advanced Packaging

Peer foundation layer: Substrates & Interposers

Architectures that depend on these interconnects: CoWoS · Foveros (Foveros Direct hybrid bonding) · 3D IC

Contrasting traditional interconnect: Bonding Overview · Flip-Chip Bonding