CPU families
CPU Families, Products and Process
| Family | Current products | Process | Supplier and architecture |
|---|---|---|---|
| AMD EPYC (server) | EPYC 9005 Turin (Zen 5 and Zen 5c); EPYC Venice (Zen 6, 2026) | TSMC N4P and N3 compute dies with a TSMC N6 I/O die (Turin); TSMC N2 (Venice) | AMD, fabless, x86; chiplet design since EPYC Rome in 2019 |
| Intel Xeon 6 (server) | Granite Rapids (P-cores); Sierra Forest and Clearwater Forest (E-cores, up to 288 cores); Diamond Rapids reported for 2027 | Intel 3 (Granite Rapids, Sierra Forest); Intel 18A (Clearwater Forest) | Intel IDM, x86; EMIB and Foveros multi-die packaging |
| Apple M-series (client) | M5 family (2025) | TSMC N3P; Ultra parts join two dies with TSMC's UltraFusion bridge | Apple, in-house Arm design; CPU, GPU and neural engine on one die |
| AMD Ryzen (client) | Ryzen 9000 (Zen 5) desktop; Ryzen AI laptop chips with an NPU | TSMC N4P compute die; TSMC N6 I/O die | AMD, fabless, x86 |
| Intel Core Ultra (client) | Core Ultra series 3 Panther Lake (2026); Arrow Lake and Lunar Lake | Intel 18A (Panther Lake compute tile); TSMC N3B compute tiles on Arrow Lake and Lunar Lake | Intel; mixes its own fabs and TSMC tiles with Foveros 3D stacking |
| Qualcomm Snapdragon X (client) | Snapdragon X2 Elite (Oryon cores) for Windows on Arm | TSMC 3nm class | Qualcomm, fabless, Arm; Oryon cores came with the 2021 Nuvia purchase |
| Cloud Arm (server) | AWS Graviton4; Microsoft Cobalt; Google Axion; NVIDIA Grace and Vera; Ampere AmpereOne | TSMC N5 and N3 class | Each cloud designs its own chip for its own data centers; Ampere was bought by SoftBank in 2025 |
| China (server and client) | Hygon C86; Loongson 3C6000 (LoongArch); Huawei Kunpeng; Phytium | SMIC and other Chinese foundries; Hygon x86 rights trace to a 2016 AMD joint venture | Hygon and Phytium are on the US Entity List; Loongson uses its own LoongArch instruction set |
| RISC-V (emerging) | SiFive P870; Ventana Veyron; Alibaba T-Head XuanTie; SpacemiT | TSMC N5 to N7 for high-performance cores; mature nodes for embedded cores | Open instruction set; China invests heavily as a hedge against x86 and Arm controls |
Supply risk
Deployment and Supply Risk
| Platform | Where it is used | Primary supply risk |
|---|---|---|
| AMD EPYC | Cloud servers, HPC, host CPU in AI clusters | TSMC N3 and N2 allocation shared with AI accelerators; separate N6 I/O die dependency |
| Intel Xeon | Enterprise servers, AI host, telecom | Intel 18A yield and ramp; Diamond Rapids timing |
| Apple M-series | Macs and on-device AI | TSMC N3P concentration; no second source |
| Cloud Arm | Cloud instances, AI hosts (Grace, Vera) | TSMC N5 and N3; Arm license dependency |
| China CPUs | Government, telecom and domestic cloud servers | SMIC capacity and export controls on tools and EDA |
Chiplets
Chiplets Split One CPU Across Several Nodes
AMD separated compute dies from the I/O die with EPYC Rome in 2019: compute at the leading edge, I/O at an older, cheaper node, joined on an organic substrate. Smaller dies yield better, and only the transistors that need the leading edge pay for it. Intel followed with tiles joined by EMIB (Sapphire Rapids) and Foveros 3D stacking (Meteor Lake), and Apple joins two M-series dies with its UltraFusion bridge.
One CPU now depends on several nodes and a packaging line. An EPYC Turin needs TSMC N4P or N3 compute dies and a TSMC N6 I/O die; Intel Arrow Lake needs a TSMC compute tile plus Intel's own base die and Foveros assembly. Chiplets also add demand for ABF substrates and advanced packaging, the same pools AI accelerators draw on. Packaging detail is on EMIB, Foveros and Advanced Packaging.
Bottlenecks
CPU Supply Chain Bottlenecks
| Bottleneck | Affects | Severity |
|---|---|---|
| TSMC N3 and N2 allocation shared with AI chips | AMD EPYC Turin and Venice, Apple M5, cloud Arm CPUs, Qualcomm | Medium-high: AI accelerators get priority on the same wafers |
| Intel 18A ramp | Clearwater Forest, Panther Lake, Intel Foundry credibility | High: Intel's server and foundry plans both depend on it |
| ABF substrate and advanced packaging | Chiplet CPUs competing with AI accelerator packaging | Medium: shared substrate supply |
| Arm license dependency | Apple, Qualcomm, AWS, Microsoft, Google, NVIDIA, Ampere | Structural: Arm (SoftBank) controls the instruction set; RISC-V is the long-term hedge |
| Export controls | Hygon, Loongson, Kunpeng, Phytium | High for China: limited access to TSMC, EUV tools and US EDA |
Record
Page Record
- Covers
- Server, client, cloud Arm and Chinese CPUs, their process nodes, packaging and supply risk
- Sources
- Mercury Research via Tom's Hardware (May 2026); AMD, Intel, Apple, Qualcomm, AWS, Microsoft, Google and NVIDIA product disclosures; US Entity List
- Last verified
- October 2026