SemiconductorX > Fab & Assembly > Manufacturing Flow > Front-End Fabrication > Wafer Etching
Wafer Etching
Etching is the pattern-transfer counterpart to deposition in the layer-build loop. Where deposition adds material, etch selectively removes it. After photolithography defines a pattern in the photoresist, etch transfers that pattern into the underlying film — the resist protects the regions that stay, the exposed regions are chemically or physically removed. Every patterned layer of the chip requires at least one etch step; a leading-edge logic chip passes through etch tools more than 100 times over its fab cycle. Etch runs alongside deposition and lithography as one of the three workhorse categories of front-end processing by tool count, wafer time, and capital investment.
The concentration story in etch sits at two vendors. Lam Research leads the etch market globally, with particular strength in high-aspect-ratio etch for 3D NAND memory and in advanced dielectric and metal etch for leading-edge logic. Tokyo Electron holds the second position, with strong presence in conductor etch and integrated coater-developer-etch flows. Applied Materials has a smaller but meaningful etch position through integrated deposition-etch platforms. Below that tier, Hitachi High-Tech, Plasma-Therm, SPTS (KLA), and Chinese domestic suppliers (NAURA, AMEC) serve specialty and mature-node applications. The Lam-TEL duopoly at the leading-edge has tightened as 3D NAND stacking and gate-all-around transistor architectures have pushed etch technology complexity beyond what competing vendors can economically match.
Etch Methods
Etching divides into two fundamental approaches. Wet etch uses liquid chemistries that react with the target material; it remains the method of choice for isotropic removal, bulk silicon etch, and specific chemistry-selective applications. Dry etch uses plasma to ionize and/or chemically activate gas-phase etchants; it dominates modern patterning because it achieves the anisotropic (directional) etch profiles that small features require. Advanced nodes add atomic layer etch (ALE), which uses self-limiting chemistry cycles to remove material one atomic layer at a time.
| Method | Mechanism | Primary Use |
|---|---|---|
| Wet etch | Liquid chemistry dissolves target material; isotropic (etches in all directions) | Bulk silicon etch, oxide strip, sacrificial layer removal, post-etch cleanup |
| Reactive Ion Etch (RIE) | Plasma generates reactive ions that bombard and chemically react with the wafer surface | General anisotropic pattern etch; workhorse across logic and memory |
| Inductively Coupled Plasma (ICP) etch | High-density plasma with independent control of ion energy and density | High-selectivity anisotropic etch; advanced-node critical layers |
| Capacitively Coupled Plasma (CCP) etch | Parallel-plate plasma configuration with RF bias | Dielectric etch, contact and via etch, high-aspect-ratio memory structures |
| High-aspect-ratio etch (HAR) | Specialized CCP etch tuned for deep vertical structures | 3D NAND channel holes (now exceeding 10 µm deep); DRAM capacitor etch |
| Atomic Layer Etch (ALE) | Self-limiting cycles of surface modification and controlled removal | Sub-5 nm transistor patterning, GAA nanosheet release, damage-sensitive structures |
| Cryogenic etch | Plasma etch at cryogenic wafer temperatures (-100 °C range) | High-aspect-ratio etch with improved profile control; growing 3D NAND adoption |
What Gets Etched
Etch chemistry and process parameters are tuned to the specific material being removed. Different materials require different gas chemistries, different ion energies, and different selectivity profiles.
| Target Material | Typical Etch Chemistry | Application |
|---|---|---|
| Silicon (Si) | Fluorine-based (SF₆, CF₄); chlorine-based (Cl₂, HBr) for anisotropic | STI trench, gate etch, deep silicon etch for MEMS and TSVs |
| Silicon dioxide (SiO₂) | Fluorocarbon (CF₄, C₄F₈, CHF₃) | Contact and via etch; dielectric patterning; STI oxide |
| Silicon nitride (Si₃N₄) | Fluorocarbon with H₂ or O₂; hot phosphoric acid (wet) | Spacer etch, nitride liner removal, pad nitride strip |
| Polysilicon | HBr + Cl₂ + O₂ mixtures | Gate electrode etch; 3D NAND word line etch |
| Metals (Al, Cu, W, Co) | Cl₂-based for Al; WF₆ / F-based for W; wet or ALE for Cu (Cu does not etch well in plasma) | Interconnect patterning; contact fill etch-back; damascene cleanup |
| High-k dielectrics (HfO₂) | Chlorine-based with careful selectivity control; ALE increasingly used | HKMG gate stack patterning |
| Low-k dielectrics (SiOCH) | Fluorocarbon with reduced damage chemistry; ALE for advanced nodes | BEOL interconnect patterning; sensitive to plasma damage |
| Photoresist | Oxygen plasma (ashing) | Post-etch resist strip; covered under Resist Strip |
Atomic Layer Etch (ALE)
Atomic layer etch is the etch counterpart to atomic layer deposition. Where conventional plasma etch removes material continuously, ALE operates in self-limiting cycles: a first step chemically modifies the top atomic layer of the target material, then a second step removes only the modified layer. Because each cycle is self-limiting, the etch depth per cycle is fixed and reproducible at atomic precision. Running multiple cycles allows controlled removal of any depth one atomic layer at a time, with minimal damage to underlying layers.
ALE has become essential for advanced-node transistor patterning. Gate-all-around (GAA) nanosheet transistors require precise release of the silicon channels from sacrificial SiGe layers, with sub-nanometer control over the released nanosheet geometry — ALE achieves this where conventional etch cannot. 3D NAND stair-step etch, which requires uniform stepped patterns across hundreds of word-line layers, increasingly uses ALE for the critical steps. Advanced DRAM capacitor structures, high-k gate etch, and damage-sensitive low-k dielectric patterning all drive growing ALE adoption. The tradeoff is throughput: ALE is slower per unit depth than conventional etch, so it is applied selectively to the critical layers where its precision justifies the cycle-time cost.
ALE equipment concentrates at Lam Research (introduced ALE into production platforms first and holds a strong lead), Tokyo Electron (ALE modules for sub-5nm applications), and Applied Materials (ALE within integrated etch-deposition platforms). The market for ALE is growing faster than conventional etch, tracking the node-advancement and 3D-NAND-layer-count curves.
Etch Equipment Vendors
| Vendor | HQ | Primary Strengths |
|---|---|---|
| Lam Research | United States | Market leader in etch globally; dominant in 3D NAND high-aspect-ratio etch; ALE leader; strong dielectric and metal etch |
| Tokyo Electron (TEL) | Japan | Second globally in etch; strong conductor etch; integrated lithography-etch flows; ALE development |
| Applied Materials | United States | Integrated etch-deposition platforms; specialty dielectric etch; ALE within cluster tools |
| Hitachi High-Tech | Japan | Specialty etch tools; strong position in memory etch at Japanese IDMs |
| Plasma-Therm | United States | Compound semiconductor etch (GaN, SiC, GaAs); MEMS and advanced packaging etch |
| SPTS (KLA) | UK (KLA subsidiary) | Specialty etch for MEMS, advanced packaging, and power devices; TSV etch |
| NAURA | China | Chinese domestic etch tools for mature-node capacity; largest Chinese WFE vendor |
| AMEC (Advanced Micro-Fabrication Equipment) | China | Chinese domestic etch leader; dielectric etch for memory and logic at Chinese fabs |
Etch Gas Supply
Etch consumes a wide range of specialty gases — fluorocarbons (CF₄, C₄F₈, CHF₃, C₄F₆), chlorine (Cl₂), hydrogen bromide (HBr), boron trichloride (BCl₃), sulfur hexafluoride (SF₆), tungsten hexafluoride (WF₆), and many more. Each chemistry is qualified per tool, per process, and often per layer. Supply concentrates at specialty gas suppliers below the bulk-gas oligopoly: Resonac (formerly Showa Denko), Kanto Denka Kogyo, Central Glass, SK Materials, and specialty suppliers like Versum/Merck. See Process Gases for the upstream view.
Neon and other rare gases used in excimer lasers for plasma generation have their own concentration story — Ukraine was historically a major neon source, and Russia-Ukraine conflict disruption has reshaped rare gas supply since 2022. Fluorine-based etch gas supply carries environmental and regulatory attention because several fluorinated compounds have very high global warming potential; abatement equipment and reduced-emission chemistry development are active areas.
Why Etch Complexity Keeps Growing
Etch has scaled in complexity faster than lithography over the past decade. Three trends drive this. First, 3D NAND scaling from 64 layers to 232+ layers has required etch tools to produce channel holes more than 10 µm deep with vertical profiles held to nanometer accuracy — an aspect ratio above 100:1, which was considered physically impossible a decade ago. Second, gate-all-around transistor architectures at 2nm and below require multiple etch steps to release the nanosheet channels from sacrificial SiGe layers, each with exacting selectivity requirements. Third, multi-patterning at DUV (for sub-7nm without EUV) multiplies every lithography step into multiple etch steps. The combined effect is that etch's share of wafer fab equipment capex has grown roughly in line with deposition, and faster than lithography. Lam Research's revenue trajectory reflects this directly — the etch leader has outpaced overall WFE growth through multiple recent cycles.
Related Coverage
Parent: Front-End Fabrication
Peers in front-end: Wafer Cleaning · Oxidation · Deposition · Photolithography · Doping · CMP · Metallization · Metrology
Equipment & consumables: WFE Hub · Process Consumables · Process Gases