Pattern transfer
Etch Turns the Resist Pattern Into Structure
Etch is how a lithography pattern becomes a physical structure. The developed resist covers the parts of the film that stay; etch removes the film wherever the resist is open, and then the resist is stripped. Every patterned layer needs at least one etch step, and a leading-edge logic wafer passes through etch chambers more than 100 times.
Two properties decide whether an etch works. Anisotropy is how straight the walls are: a wet etch eats sideways as fast as down and undercuts the mask, while a plasma etch drives ions vertically. Selectivity is how much faster the target film etches than the resist and the layer beneath it; at advanced nodes the films are a few nanometers thick, so an etch must stop on an underlayer it barely differs from.
Methods
Plasma Etch Does Nearly All Patterning
| Method | Mechanism | Primary use |
|---|---|---|
| Wet etch | Liquid chemistry dissolves the film in all directions | Oxide strip, sacrificial layer removal, bulk silicon, post-etch cleanup |
| Reactive ion etch (RIE) | Plasma ions bombard the surface while radicals react with it | General anisotropic pattern etch in logic and memory |
| Inductively coupled plasma (ICP) | High-density plasma with ion energy controlled separately | Silicon, gate and metal (conductor) etch at critical layers |
| Capacitively coupled plasma (CCP) | Parallel-plate plasma with high ion energy | Dielectric etch: contacts, vias, DRAM capacitors and NAND channel holes |
| Deep reactive ion etch (DRIE) | Alternating etch and passivation (Bosch process) | MEMS, through-silicon vias and power devices |
| Cryogenic etch | Plasma etch with the wafer chilled well below freezing | High-aspect-ratio 3D NAND channel holes |
| Atomic layer etch (ALE) | Self-limiting cycles of surface modification and removal | Gate-all-around and other few-nanometer steps |
| Ion beam etch and milling | Physical sputtering by an ion beam | MRAM stacks, magnetic heads and materials that do not form volatile products |
| Plasma ash | Oxygen plasma oxidizes organic resist | Resist strip; see Photoresist and Development |
Plasma etch does nearly all patterning today. Wet etch survives where its isotropy helps: removing whole layers, undercutting sacrificial films, and cleaning after a dry etch.
Memory etch
3D Memory Needs Holes 50 Times Deeper Than Wide
3D NAND stacks hundreds of word-line layers and then etches a channel hole through all of them. The hole is about 10 µm deep and more than 50 times deeper than it is wide, and it has to stay round and straight from top to bottom while ions lose energy on the way down. Makers now split the stack into two or three decks, etching each separately, to keep holes within tolerance.
- Cryogenic etch: chilling the wafer changes the surface chemistry so the walls passivate and the etch front keeps moving. Lam's Cryo 3.0 (2024) holds critical-dimension deviation below 0.1% through a 10 µm hole; of more than 7,500 Lam high-aspect-ratio dielectric etch chambers in NAND production, nearly 1,000 ran cryogenic etch at launch.
- Layer counts: SK hynix plans 321-layer QLC NAND shipments in the second half of 2026, and Samsung's V10, reported at about 430 layers, is due in the same period. The industry target is about 1,000 layers by 2030.
- DRAM: capacitor holes in DRAM are the other high-aspect-ratio etch, and get deeper each generation as cells shrink.
Every added deck and layer adds etch time per wafer, which is why memory spending lifts etch tool sales more than any other category. NAND fabs are on 3D NAND Fabs.
Gate-all-around
Gate-All-Around Adds Sideways, Selective Etch
Gate-all-around (GAA) transistors, in volume at TSMC N2, Intel 18A (RibbonFET) and Samsung SF2, are built from a stack of alternating silicon and silicon-germanium layers. A selective etch removes the silicon-germanium between the sheets while leaving the silicon almost untouched, and the gate fills the gaps. Inner spacers, source and drain recesses and the release itself are all lateral, selective etches that a FinFET did not need.
Lam (Selis, Argos and Prevos), Applied Materials (Selectra) and Tokyo Electron sell dedicated selective-etch chambers for these steps, and atomic layer etch handles the thinnest. Node detail is on Process Nodes.
Tool makers
Lam and Tokyo Electron Lead Etch
| Company | Strength | Position |
|---|---|---|
| Lam Research (US) | Dielectric and conductor etch; high-aspect-ratio memory etch; cryogenic etch | Market leader; dominant in NAND and DRAM etch |
| Tokyo Electron (Japan) | Dielectric etch, integrated track-etch flows | Second; strong in DRAM and logic dielectric |
| Applied Materials (US) | Conductor and selective etch (Centris, Selectra) | Third; strength in logic |
| Hitachi High-Tech (Japan) | Microwave ECR conductor etch | Specialist in logic gate etch |
| AMEC (China) | CCP dielectric and ICP etch | Volume production on DRAM steps at CXMT; high-aspect-ratio etch in qualification |
| Naura (China) | ICP silicon and metal etch | Broad mature-node coverage in China |
| SPTS (KLA), Plasma-Therm, Oxford Instruments | DRIE, compound semiconductor and MEMS etch | Specialty and mature-node fabs |
- Made in US
- Some US volume
- US planned
- Made abroad
| Site | Location | Makes | Status | US status |
|---|---|---|---|---|
| Lam Research Fremont | Fremont, CA | Etch and deposition systems; headquarters and manufacturing | Operating | Made in US |
| Lam Research Tualatin | Tualatin, OR | Etch and deposition systems | Operating | Made in US |
| Lam Research Batu Kawan | Penang, Malaysia | Etch and deposition systems; Lam's largest plant | Operating | Made abroad |
| Tokyo Electron Miyagi | Miyagi, Japan | Plasma etch systems | Operating | Made abroad |
| Hitachi High-Tech Kasado | Yamaguchi, Japan | Conductor etch systems | Operating | Made abroad |
| AMEC | Shanghai and Nanchang, China | CCP and ICP etch systems | Operating; expanding | Made abroad |
| Naura | Beijing, China | ICP etch, deposition and clean systems | Operating; expanding | Made abroad |
| Placeholder: other etch tool plants | ||||
Lam and Tokyo Electron hold most of the leading-edge market, and the gap widened as 3D NAND and gate-all-around raised the difficulty of each step. Lam's fiscal 2026 annual report names Applied Materials, Hitachi and Tokyo Electron as its main etch competitors. Tool detail is on Etch Equipment.
China
Etch Is China's Strongest Tool Category
Etch is where China's own toolmakers are furthest along. AMEC had revenue of RMB 12.4 billion in 2025, up 37%, and had shipped more than 6,800 process chambers by the end of the year; its CCP etch systems run in volume production on several DRAM steps at CXMT, and its high-aspect-ratio systems are in production-line qualification. Naura covers ICP etch alongside deposition and clean. US export rules restrict Lam, Applied and KLA tools for advanced Chinese fabs, which pushes YMTC and CXMT toward domestic etch.
Etch gases
Etch Runs on Fluorine and Chlorine Chemistry
| Gas | Used for |
|---|---|
| CF4, C4F8, C4F6, CHF3 | Oxide and nitride dielectric etch |
| SF6, NF3 | Silicon etch, chamber cleaning |
| Cl2, BCl3, HBr | Polysilicon, metal and silicon etch |
| O2 | Resist ash and polymer removal |
| Ar, He | Dilution and physical sputtering |
Fluorinated etch gases are potent greenhouse gases; fabs abate them at the exhaust, and climate rules on several of them are tightening. Supply and makers are covered on Process Gases.
Record
Page Record
- Covers
- Pattern transfer, etch methods, high-aspect-ratio memory etch, gate-all-around release, tool makers, China and etch gases
- Sources
- Lam Research (Cryo 3.0 release, August 2024; fiscal 2026 Form 10-K); TrendForce (SK hynix and Samsung NAND plans, November 2025; AMEC 2025 results, August 2026); Counterpoint Research (1,000-layer NAND outlook); company site lists for plant locations
- Last verified
- October 2026