2.5D Packaging

2.5D is the umbrella category for advanced packaging architectures that place multiple dies side-by-side on a shared interconnect layer — the interposer. Where traditional flip-chip packaging places a single die on a substrate and where 3D IC stacks dies vertically, 2.5D arranges dies laterally with a shared routing plane underneath that handles the die-to-die signals at bandwidth impossible through an organic substrate alone. The ".5" in the name captures that geometric position: it's not 2D (single plane) and not 3D (stacked), but a middle layer of integration where multiple dies share a plane but still communicate at near-3D interconnect density through the interposer.

2.5D is the workhorse architecture for AI accelerators, HPC processors, high-bandwidth networking ASICs, and any product that integrates High Bandwidth Memory (HBM) alongside compute logic. TSMC CoWoS is the volume leader and the binding supply constraint on the global AI accelerator market. Intel EMIB is the bridge-based variant used across Intel FPGA, server CPU, and HPC products. Samsung I-Cube is Samsung Foundry's 2.5D offering with captive HBM integration. Each has its own page covering the architecture-specific detail; this page is the category umbrella that defines what 2.5D is, maps the landscape, and frames what's common across all 2.5D implementations.

The three major 2.5D architectures run captive at the three major foundries, with no merchant OSAT operator at equivalent scale. This structural pattern — foundry-captive production across the leading-edge tier — is one of the defining features of 2.5D packaging and is part of why 2.5D capacity is tightly coupled to foundry capacity planning.

Why 2.5D Exists Between Traditional and 3D

2.5D fills an architectural and economic gap between traditional flip-chip FCBGA (cost-efficient but bandwidth-limited) and 3D die-stacking (highest density but with severe thermal and yield constraints). The three positions serve different products, and the gap 2.5D fills is real rather than marketing.

The differentiators are geometric and drive the application mapping. 2.5D is the natural fit when a product needs high-bandwidth die-to-die integration (especially HBM-plus-logic) but cannot tolerate 3D's thermal penalty — an AI accelerator with 8 HBM stacks and 700W+ compute power cannot reasonably stack the HBM on top of the compute die because the thermal path through stacked HBM would collapse performance. Spreading the HBM and compute laterally on a 2.5D interposer distributes the thermal load across a larger footprint while preserving the die-to-die bandwidth needed for the integrated system.

The Three Interposer Types

2.5D architectures differ primarily in the type of interposer that carries the die-to-die routing. The three interposer types span the cost-and-performance spectrum within 2.5D.

Full silicon interposer is the highest-performance option. Interposers are fabricated on silicon wafers using back-end-of-line processes similar to front-end interconnect formation — damascene copper routing, TSVs, CMP, dielectric deposition. The resulting routing density matches the finest metal layers of the foundry's own logic process, enabling direct die-to-die connections at thousands of signals per mm² at the die interface. Full silicon interposers are also the most expensive option per module because the interposer consumes substantial silicon area.

Silicon bridges solve the cost problem by observing that most of a 2.5D module doesn't need silicon-interposer density — only the specific zones where two dies need high-bandwidth communication. Embedding small silicon bridges (tens of square millimeters each) exactly at those zones, and using organic substrate routing everywhere else, delivers the bandwidth where needed at a fraction of the total silicon cost. EMIB is the production incumbent of the bridge approach; CoWoS-L and I-Cube-E are newer additions at TSMC and Samsung applying the same concept within those foundries' 2.5D portfolios.

RDL interposers sit in the middle — thin-film copper routing on an organic carrier with line/space narrower than standard substrate but wider than silicon interposer BEOL. CoWoS-R is the primary RDL-interposer 2.5D variant. RDL serves customers who need better bandwidth than standard FCBGA but don't require (or can't afford) full silicon-interposer density.

The 2.5D Architecture Landscape

The named 2.5D architectures map across the three major foundries and (with bridge variants) the OSAT tier. Each architecture has its own page with the architecture-specific detail; the table below is the orientation index.

The 2.5D landscape is structurally symmetric across the three major foundries: each offers a full silicon interposer platform plus a bridge variant plus (in TSMC's case) an RDL variant. The convergence is not coincidence — each foundry has followed roughly parallel architectural evolution in response to similar customer pressure (higher bandwidth, HBM integration, AI accelerator demand, cost optimization). OSATs are extending the bridge approach down-market with platforms like FOCoS-Bridge.

Shared Process Elements

Every 2.5D architecture shares a common set of process elements regardless of which operator runs it.

The distinctive element of 2.5D relative to traditional packaging is the interposer fabrication step. Full silicon interposer fabrication uses essentially front-end processes — deep silicon etch for TSVs, damascene copper routing, CMP, dielectric deposition — performed at the foundry's advanced packaging facilities. This is why 2.5D production is foundry-captive: the interposer is effectively a silicon-process product that must come from a fab-grade facility, and co-locating interposer fabrication with logic die fabrication enables process co-optimization that external OSATs cannot match for the leading-edge tier.

HBM Integration as the Archetypal 2.5D Use Case

HBM integration is the use case that drove 2.5D from specialty technology to mainstream advanced packaging. HBM stacks carry over 1,000 signal pins per stack; integrating 2-8 HBM stacks alongside a logic die requires thousands to tens of thousands of fine-pitch connections between the HBM and logic. No organic substrate can route this density; the only viable architectural answer has been 2.5D with a silicon interposer (or silicon bridge zones under each HBM-to-logic interface).

Every commercially shipping AI accelerator uses 2.5D for this integration: NVIDIA H100/H200/B-series/Rubin on CoWoS-S; AMD MI300/MI400 on CoWoS-S; Intel Sapphire Rapids HBM variant on EMIB; Samsung Foundry customers on I-Cube; hyperscaler custom AI silicon across the 2.5D options. The HBM-plus-logic pattern is so central that 2.5D capacity planning at each foundry tracks HBM stack volume growth directly — every additional HBM stack in an AI accelerator module consumes additional interposer area and advanced packaging capacity.

The evolution of HBM generations (HBM3 → HBM3E → HBM4) drives parallel evolution in 2.5D: larger interposers to accommodate more HBM stacks, finer-pitch micro-bumps or hybrid bonding at the HBM-to-interposer interface, thermal designs managing higher per-module power, and beyond-reticle interposer capability as modules exceed photolithography reticle limits. See HBM for the memory-side view and CoWoS for the architecture-specific treatment of the 2.5D side.

2.5D vs. 3D Going Forward

2.5D and 3D are not directly competitive — they serve different integration purposes. 2.5D excels at integrating high-bandwidth memory (HBM) alongside compute at thermal profiles that stacking would not allow. 3D excels at stacking logic on logic at the shortest possible interconnect distances. Most next-generation high-performance modules will use both: 2.5D for the logic-plus-HBM integration at the module level, plus 3D (SoIC, Foveros Direct, SAINT) within the logic portion for die-on-die stacking of compute tiles, cache, or accelerators.

The forward trajectory across both categories is toward hybrid bonding as the universal die-to-die interconnect technology at the finest pitches. 3D architectures have adopted hybrid bonding first (SoIC, Foveros Direct, HBM4). 2.5D architectures are now beginning the transition — future 2.5D generations will likely use hybrid bonding at the HBM-to-interposer interface where today's designs use micro-bumps. This transition will put additional demand on the already-constrained hybrid bonding equipment supply (BESI-Applied Materials, Tokyo Electron).

Market Outlook

2.5D demand is driven by the AI accelerator production ramp, HBM-per-module count growth, hyperscaler custom silicon programs, and the broader spread of HBM integration into server CPUs and specialty compute. Through this decade, 2.5D is expected to remain the dominant advanced packaging architecture by revenue (even if 3D grows faster in percentage terms), because the HBM-plus-logic integration pattern that 2.5D enables is the defining architectural pattern of AI accelerator silicon.

Capacity expansion is concentrated at the three major foundries and proceeds alongside each foundry's broader advanced packaging buildout. TSMC CoWoS capacity is the most visible constraint, roughly doubling annually while demand continues to outrun supply. Samsung I-Cube and Intel EMIB expand alongside their respective foundry roadmaps. The bridge-based 2.5D tier (EMIB, CoWoS-L, I-Cube-E, FOCoS-Bridge) is the fastest-growing subcategory by customer count, driven by customers who cannot secure premium full-interposer capacity but need multi-die integration at moderate bandwidth.

Related Coverage

Parent: Advanced Packaging

2.5D architecture pages: CoWoS · EMIB · I-Cube

Peer 3D umbrella: 3D IC

Foundation layers: Substrates & Interposers · Advanced Interconnects

Related OSAT-tier approaches: FO-WLP (FOCoS-Bridge)

Cross-architecture reference: Comparison Matrix

Cross-pillar dependencies: HBM (archetypal 2.5D consumer) · AI Accelerators · Bottleneck Atlas