Multi-Chip Modules (MCMs)

A multi-chip module integrates two or more dies onto a common substrate, presenting to the system as a single component. The substrate provides the electrical interconnect between the dies, the mechanical platform, and the thermal interface to the heat spreader or cold plate. MCMs sit structurally between advanced packaging (which integrates dies with sub-10 µm interconnect pitches on silicon interposers or through hybrid bonding) and subsystem board assembly (which places packaged components onto a multi-layer PCB). The distinction is the substrate: MCMs use organic laminate substrates or 2.5D interposers with die-to-die interconnects at micron-scale pitches, whereas boards use PCBs with package-to-package connections at millimeter scale.

MCMs have become the dominant integration strategy for leading-edge CPUs, GPUs, and AI accelerators because monolithic die scaling has hit a reticle-limit ceiling of roughly 858 mm². Beyond that size, lithography cannot pattern the die in a single exposure — any larger chip must be built from multiple smaller dies combined later. AMD demonstrated the commercial viability of the chiplet approach with its EPYC processors starting in 2017; NVIDIA, Intel, AMD (MI300), Apple (M1 Ultra), and others have since committed to multi-die integration as the default approach. The Advanced Packaging methods (CoWoS, Foveros, EMIB) are the enabling technologies that make high-bandwidth die-to-die communication fast enough to keep multi-die CPUs and GPUs competitive with the monolithic designs they replace.

Why Multi-Die Integration Is Now Dominant

Three forces have pushed the industry to multi-die integration. First, reticle-limit scaling: the largest die that can be patterned in a single EUV exposure is approximately 26 mm × 33 mm. Any chip larger than that must be built from multiple dies, which forces the architecture choice. Second, yield economics: a single large monolithic die has yield that falls exponentially with area because a single defect anywhere on the die scraps the whole chip. Splitting the same function across smaller dies dramatically improves yield, because defects only scrap individual dies and the remaining good dies can still be assembled. For example, four 400 mm² chiplets combined into a module yield far better than one 1600 mm² monolithic die. Third, heterogeneous integration: different functions benefit from different process nodes. A CPU compute die benefits from leading-edge logic (N3 or N2); an I/O die can use mature 7 nm at half the cost; memory benefits from its own dedicated process. MCMs let each function run on its ideal node.

The tradeoff is die-to-die communication. Two dies on a substrate must communicate across an interface that is orders of magnitude slower and higher-power than on-die wire. The engineering work of MCM integration is principally about making that interface fast and efficient enough that the multi-die assembly matches the performance of the monolithic chip it replaces. The fabrics that do this — NVLink-C2C, Infinity Fabric, UCIe — are discussed below.

MCM Substrate Types

MCMs divide by substrate technology, which defines the achievable die-to-die bandwidth, integration density, and cost.

Die-to-Die Fabrics

The die-to-die interconnect fabric determines how much performance is lost compared to monolithic integration. The fabric spec covers signaling protocol, physical layer (serializer-deserializer design), bump pitch, and power per bit. Current fabrics achieve die-to-die bandwidth in the terabits-per-second range at power efficiencies approaching on-die levels.

UCIe is the key standardization effort. If it succeeds, chiplets from different vendors at different process nodes could be combined into a single MCM by a third-party integrator — for example, an AMD compute chiplet with a third-party I/O chiplet and a memory chiplet from yet another vendor. The open chiplet ecosystem that UCIe enables would substantially change semiconductor economics, though current production remains largely within single-vendor MCMs.

Representative MCMs

MCM Assembly

MCM assembly happens primarily at foundries (for leading-edge compute MCMs that use advanced packaging technologies) and at OSATs (for organic-substrate MCMs and specialty applications). The steps involve known-good-die screening (confirming each die works before integration, since a bad die wasted inside an MCM scraps the entire module), flip-chip attach of dies to substrate, underfill, molding, final test. MCMs with silicon interposers or advanced packaging technologies follow the flows described under Advanced Packaging. MCMs with organic substrates share much of the flow with traditional back-end assembly, with the substrate playing a larger interconnect role.

Substrate supply is its own concentration story. Ajinomoto Build-up Film (ABF), the organic substrate material that supports fine-line routing on nearly all modern CPU and GPU organic MCMs, is produced by a single company (Ajinomoto) and has been a supply chokepoint multiple times over the past decade. Substrate fabrication concentrates at Unimicron, Nan Ya PCB, Ibiden, Shinko Electric, and a small number of other specialty substrate makers in Taiwan and Japan. This is covered in more depth under Substrates & Interposers.

Thermal and Power Density

Modern MCMs exceed 1000 watts total package power for top-end AI accelerators. Delivering that power requires multi-layer organic substrates routed for hundreds of amperes at millivolt precision, and the voltage regulator modules (VRMs) that feed those substrates are themselves significant components of the subsystem board. Removing that power as heat requires integrated heat spreaders, vapor chambers, and in leading applications direct-liquid cooling plates attached to the module. Warpage and coefficient-of-thermal-expansion (CTE) mismatch between silicon dies and organic substrates are ongoing engineering challenges that become more severe as modules get larger. These thermal and mechanical constraints are increasingly the bounding factor on how much compute can be packed into a single module.

Related Coverage

Parent: Module Integration

Sibling modules: Memory Modules · CPU/GPU Boards

Enabling technologies (Advanced Packaging): Advanced Packaging · CoWoS · Foveros · Substrates & Interposers

Assembly operators: OSAT Landscape

Cross-pillar dependencies: HBM · AI Accelerators · Bottleneck Atlas