Advanced Packaging Overview

Fan-out · 2.5D · 3D · substrates · hybrid bonding

Advanced packaging joins logic, memory and I/O dies into one module, and it was a $46 billion market in 2024, heading past $79 billion by 2030 (Yole). Every flagship AI accelerator is assembled on TSMC CoWoS in Taiwan, on substrates built from Japanese film, around HBM from Korea; no CoWoS-class line produces in the United States until Amkor's Peoria, Arizona plant opens in 2028.

Cross-section of an AI accelerator package built on TSMC CoWoS-L: two logic dies and four HBM stacks on a TSMC interposer with silicon bridges, on an ABF organic substrate, on the board. HBM comes from SK hynix, Samsung and Micron in Korea, Taiwan and Japan; logic dies and the interposer from TSMC in Taiwan; the substrate from Ibiden and Unimicron on Ajinomoto film; assembly and test in Taiwan. Only the logic die has any US production, at TSMC Arizona, and those wafers are packaged in Taiwan. AN AI ACCELERATOR PACKAGE, LAYER BY LAYER (COWOS-L) LOGIC HBM STACKS HBM STACKS HBM stacks SK HYNIX, SAMSUNG, MICRON KOREA, TAIWAN, JAPAN Logic dies TSMC N4P / N3 TAIWAN; SOME N4 AT TSMC ARIZONA Interposer and bridges TSMC COWOS-L TAIWAN Package substrate IBIDEN, UNIMICRON; AJINOMOTO FILM JAPAN, TAIWAN Assembly and test TSMC, SPIL, AMKOR; KYEC TEST TAIWAN SOME US VOLUME MADE ABROAD NOT TO SCALE
Market, 2024
$46B (Yole)
Forecast, 2030
$79B+
CoWoS, end 2026
120-140K wafers/mo
Hybrid bond pitch
6 µm, TSMC SoIC
US CoWoS-class
Amkor Peoria, 2028
Hub
Packaging

Three families

Fan-Out, 2.5D and 3D Packaging

Traditional back-end assembly wraps one die in one package. Advanced packaging joins several dies through dense wiring, in one of three ways.

The three advanced packaging families: fan-out spreads a die's connections across a molded wafer with redistribution layers; 2.5D sets dies side by side on a silicon interposer or bridge; 3D stacks dies on each other through TSVs or hybrid bonds. Fan-out INFO, FO-WLP, FOPLP DIE MOLD COMPOUND RDL, THEN SOLDER BALLS 2.5D COWOS, EMIB, I-CUBE HBM LOGIC HBM INTERPOSER ON SUBSTRATE 3D SOIC, FOVEROS, HBM STACKED DIES, TSVS THROUGH STACK ON SUBSTRATE
  • Fan-out embeds the die in a molded wafer or panel and builds redistribution layers (RDL) on top, spreading its connections over a wider area without a separate substrate.
  • 2.5D places dies side by side on a silicon interposer, an RDL interposer or small silicon bridges, which carry thousands of fine-pitch connections between logic and high-bandwidth memory (HBM).
  • 3D stacks dies on each other, joined by through-silicon vias (TSVs) and micro-bumps or by direct copper-to-copper hybrid bonds.

Transistor scaling has slowed, so the package now sets much of a chip's bandwidth, power and cost. TSMC's packaging business reached about 8% of its 2025 revenue and is expected to pass 10% in 2026.

Architectures

Named Architectures and Their Operators

Each foundry runs its own branded 2.5D and 3D platforms; outsourced assembly and test companies (OSATs) run fan-out and system-in-package (SiP) lines. The Comparison Matrix cuts the same set by method, tier and status.

  • Fan-out
  • 2.5D
  • 3D
  • System in package
Advanced packaging architectures
ArchitectureFamily and carrierOperatorStatus, October 2026
CoWoS (S, R, L)2.5D: silicon interposer, RDL interposer or silicon bridgesTSMCProduction; NVIDIA Blackwell and Rubin on CoWoS-L
EMIB and EMIB-T2.5D: silicon bridge in organic substrateIntelEMIB in production; EMIB-T in fab rollout in 2026
I-Cube2.5D: silicon interposer or bridgeSamsung FoundryProduction, small customer base
XDFOI and silicon interposer 2.5D2.5D: RDL or silicon interposerJCET; SJ Semiconductor (China)Production; SJ Semiconductor holds about 85% of China's 2.5D market
SoIC3D: hybrid bonding, die on dieTSMCProduction; AMD 3D V-Cache and MI300, Fujitsu Monaka
Foveros and Foveros Direct3D: micro-bumps; hybrid bonding in DirectIntelProduction; Foveros Direct in Clearwater Forest since 2026
SAINT3D: SRAM, logic or DRAM on logicSamsung FoundryDevelopment; hybrid-bonded HBM targeted 2029 to 2030
HBM stack3D: DRAM dies on a base die, TSVs and micro-bumpsSK hynix, Samsung, MicronHBM4 in production on micro-bumps
InFOFan-out wafer-levelTSMCProduction; Apple A- and M-series
FO-WLP and FOPLPFan-out wafer or panelASE, Amkor, JCET; TSMC CoPoS pilotProduction; TSMC panel line in pilot, volume 2028 to 2029
SiPMulti-component moduleASE, Amkor, JCET, IDMsProduction

2.5D

2.5D Carries Every AI Accelerator

An AI accelerator needs thousands of connections between its logic die and each HBM stack, more than an organic substrate can route. 2.5D answers this with a silicon layer under the dies.

  • TSMC CoWoS: CoWoS-S uses a full silicon interposer, CoWoS-R an RDL interposer and CoWoS-L silicon bridges in an RDL layer. NVIDIA Blackwell and Rubin use CoWoS-L, because their modules exceed what a single silicon interposer can hold.
  • Intel EMIB: small silicon bridges embedded in the organic substrate only where dies meet. EMIB-T adds TSVs through the bridge for HBM4-class power delivery and enters fab rollout in 2026; Intel says bridges use about 90% of a wafer against about 60% for large interposers.
  • Samsung I-Cube: silicon interposer and bridge variants for Samsung Foundry customers.
  • China: SJ Semiconductor, the SMIC and JCET joint venture listed on the STAR Market in April 2026, holds about 85% of China's 2.5D market; JCET runs its XDFOI chiplet platform.

Interposer types, process steps and HBM integration are on 2.5D Packaging.

3D and hybrid bonding

Hybrid Bonding Runs in Logic, Not Yet in HBM

Hybrid bonding joins two polished die surfaces copper to copper and oxide to oxide, with no solder, at pitches below 10 µm against 25 to 55 µm for micro-bumps.

  • TSMC SoIC: in volume since AMD 3D V-Cache and MI300; bond pitch moved from 9 µm to 6 µm, with 4.5 µm targeted by 2029.
  • Intel Foveros Direct: 9 µm pitch in the Clearwater Forest (Xeon 6+) server CPU, shipping since the first half of 2026.
  • HBM: JEDEC raised the HBM height limit from 720 to 775 µm in January 2026, which lets 16-high HBM4 keep micro-bumps. SK hynix stacks HBM4 with mass-reflow molded underfill (MR-MUF); Samsung and Micron use thermocompression with non-conductive film. Hybrid-bonded HBM is expected with HBM4E or HBM5, and Samsung has reportedly set 2029 to 2030 for volume.

Architectures, stack heat and yield are on 3D IC Packaging; the bonding technologies and tools are on Advanced Die Interconnects.

Fan-out

Fan-Out Moves From Wafers to Panels

  • TSMC InFO: the fan-out platform for Apple A-series and M-series processors, with package-on-package (InFO-PoP) and system-on-wafer (InFO_SoW) variants.
  • FO-WLP: fan-out at ASE, Amkor and JCET for phone processors, RF front ends and automotive radar.
  • Panel-level (FOPLP and CoPoS): the same process on rectangular panels for more units per run. TSMC's CoPoS pilot line in Chiayi was due for completion in June 2026, with volume expected in 2028 to 2029; warpage on large panels is the main hurdle.

Substrates

Substrates and Interposers

Carrier layers under the dies
CarrierUsed inSuppliers
Silicon interposerCoWoS-S, I-Cube-SMade at the foundry: TSMC, Samsung
Silicon bridgeEMIB, EMIB-T, CoWoS-L, I-Cube-EIntel (EMIB); TSMC (CoWoS-L local silicon interconnect)
RDL interposerCoWoS-R, fan-out, chiplet modulesFoundries and advanced OSATs
ABF organic substrate (FCBGA)Under the interposer, or directly under a flip-chip dieIbiden, Unimicron, Nan Ya PCB, Shinko, AT&S, Samsung Electro-Mechanics; ABF film from Ajinomoto
Glass core substrateNext-generation large packagesAbsolics (SKC) in Covington, Georgia, in customer qualification; Intel in development

Suppliers, lead times and glass substrates are on Substrates and Interposers.

Who packages

Leading-Edge Packaging Is Captive

Ten years ago most packaging went to OSATs. Leading-edge packaging now runs inside the companies that make the dies, because the interposer or bridge is made at the same foundry as the logic die and tuned with its process.

  • Foundries: TSMC runs CoWoS, InFO and SoIC in Taiwan; Intel runs EMIB and Foveros at Fab 9 in Rio Rancho, New Mexico, and in Malaysia; Samsung runs I-Cube and SAINT in Korea.
  • Memory makers: SK hynix, Samsung and Micron stack their own HBM.
  • OSATs: ASE (with SPIL), Amkor and JCET take CoWoS overflow, fan-out, FOPLP and SiP; Tongfu packages AMD chiplets in China.

Plants and operators are on Packaging and Test Facilities and OSAT Landscape.

Bottlenecks

Advanced Packaging Bottlenecks

Where AI accelerator packaging is constrained
BottleneckConcentrationEffect
TSMC CoWoS capacityAbout 120,000 to 140,000 wafers a month by end of 2026, all in TaiwanSets AI accelerator output for NVIDIA, AMD, Broadcom and Google
Interposer sizeRubin-class modules fit only four to seven per 300mm waferPushes TSMC toward rectangular panels (CoPoS) later this decade
HBM supplySK hynix about 50%, Samsung 33%, Micron 18% (2Q 2026)Every accelerator ships with four to 12 stacks; see HBM
ABF filmAjinomoto above 95% of the build-up film in FCBGA substratesSingle supplier under every high-pin-count package
FCBGA substratesIbiden, Unimicron, Nan Ya PCB, Shinko, AT&S, Samsung Electro-MechanicsLarge AI substrates need more layers and lose yield as they grow
Bonding toolsTC bonders: Hanmi, Hanwha Semitech, ASMPT. Hybrid bonders: Besi with Applied Materials, Tokyo ElectronGate HBM stack height and the move to hybrid-bonded logic

Who supplies each layer of a specific chip, plant by plant, is on the Chip Supplier Rings.

US packaging

US Advanced Packaging Starts in 2028

The United States holds about 3% of world packaging capacity (Bloomberg, 2023). TSMC Arizona's N4 wafers go back to Taiwan for CoWoS.

  • Intel Fab 9, Rio Rancho, New Mexico: EMIB and Foveros in production since January 2024; the only leading-edge packaging line producing in the US.
  • Amkor, Peoria, Arizona: production from early 2028 under a 10-year TSMC agreement.
  • TSMC Arizona: its own CoWoS and SoIC plant is planned before 2029.
  • SK hynix, West Lafayette, Indiana: HBM packaging from the second half of 2029.

The full plan is on US Reshoring.

What to measure

Measures of an Advanced Package

Package measures
MeasureWhat it captures
Die-to-die bandwidthGB/s or TB/s between dies; set by connection count times signal rate
Interconnect densityConnections per mm², set by bump or bond pitch
Thermal resistance°C per watt from die to lid; limits module power
Assembly yieldShare of modules that pass after bonding; one bad die can scrap the module

Record

Page Record

Covers
Packaging families, named architectures, substrates, captive and OSAT packaging, bottlenecks and US packaging plans
Sources
Yole Group (Status of the Advanced Packaging Industry 2025), TrendForce, Tom's Hardware, Counterpoint, company releases (TSMC, Intel, Samsung, SK hynix, Amkor, SJ Semiconductor)
Last verified
October 2026