Process Design Kits

PDKs, rule decks and device models · TSMC OIP, Samsung SAFE, Intel Foundry, SKY130

A process design kit is the foundry's rulebook and model set for one node, and no design yields without it. Three gates now stand between a design and a 16nm-or-below foundry: the foundry's kit, licensed EDA tools certified for it, and since January 2025 a US rule that requires an approved designer or an attestation that the chip has fewer than 30 billion transistors or no HBM.

Three gates stand between a chip design and a leading-edge foundry. First, the foundry must grant access to its process design kit under a non-disclosure agreement. Second, the designer must hold licenses for the EDA software the kit is certified for. Third, since January 2025, a US rule presumes that logic chips at 16/14nm or below need a license unless the designer is on an approved list, or the foundry or an approved packager attests that the packaged chip has fewer than 30 billion transistors or no high bandwidth memory. The threshold rises to 35 billion in 2027 and 40 billion in 2029. THREE GATES BETWEEN A DESIGN AND A 16NM-OR-BELOW FOUNDRY 1 PDK access Foundry NDA; qualified customers only TSMC, SAMSUNG, INTEL DECIDE WHO GETS N2, SF2, 18A KITS 2 EDA licenses Tools certified for that kit SYNOPSYS, CADENCE, SIEMENS FLOWS; US LICENSES FOR ENTITY LIST FIRMS 3 US due diligence rule Since January 2025, 16/14nm and below APPROVED DESIGNER, OR ATTESTATION OF THE PACKAGED CHIP GATE 3: TRANSISTOR THRESHOLD FOR THE ATTESTATION ROUTE 2025 30B transistors 2027 35B transistors 2029+ 40B transistors BELOW THE THRESHOLD, OR WITHOUT HBM, A FOUNDRY OR APPROVED OSAT MAY ATTEST INSTEAD OF SEEKING A LICENSE. BIS INTERIM FINAL RULE, JANUARY 16, 2025.
Rule threshold
16/14nm and below
Transistor limit, 2025
30B
Limit from 2029
40B
TSMC foundry share, 2Q 2026
72.5%
Open kits
SKY130, GF180, SG13G2
Hub
Materials

Access

Three Gates Stand Between a Design and a Leading-Edge Foundry

A process design kit (PDK) is the foundry's rulebook and model set for one process node: how its transistors behave, which shapes it can print, and what its wires cost in delay. A designer cannot produce a layout that will yield without it, and the foundry decides who receives it. Leading-edge kits are issued under non-disclosure agreements to qualified customers, they are certified only for particular EDA tool versions, and since January 2025 a US Commerce Department rule adds a third gate for logic chips at 16/14nm or below.

That rule, the foundry due diligence rule, presumes such chips fall under advanced computing export controls. Foundries can release a design without a license only if the designer is on an approved list, or if the foundry or an approved packaging house attests that the packaged chip has fewer than 30 billion transistors or carries no high bandwidth memory. The transistor threshold rises to 35 billion in 2027 and 40 billion in 2029. The rule turned foundries such as TSMC into the checkpoint for who can build large AI chips.

What is in a kit

Each Part of the Kit Feeds One Step of the Design Flow

What a process design kit contains and which design step uses each part. Transistor SPICE models feed circuit simulation. Standard cell libraries feed synthesis and place and route. Interconnect resistance and capacitance files feed extraction and timing. The design rule manual and the DRC and LVS rule decks feed sign-off. Technology files and validated IP feed layout and integration. Every part is calibrated to one foundry process, so a design built on one kit cannot move to another foundry without redesign. Foundry PDK, one node SPICE device models Circuit simulation SPECTRE, HSPICE, PRIMESIM Standard cell libraries Synthesis, place and route FUSION COMPILER, INNOVUS RC extraction files Extraction and timing STARRC, QUANTUS, PRIMETIME Design rules, DRC/LVS decks Physical sign-off CALIBRE, IC VALIDATOR, PEGASUS Tech files, validated IP Layout and integration VIRTUOSO, CUSTOM COMPILER Tape-out ONE FOUNDRY ONLY SCHEMATIC. TOOL NAMES ARE EXAMPLES FROM SYNOPSYS, CADENCE AND SIEMENS EDA.
What a process design kit contains
PartWhat it providesUsed in
SPICE device modelsTransistor behavior (BSIM-CMG for FinFET and gate-all-around) with process corners and statistical variationCircuit simulation, analog design, timing characterization
Standard cell librariesLogic gates and flip-flops in several drive strengths and threshold voltagesSynthesis, place and route, timing
Design rule manualMinimum widths, spacings, enclosures, density and via rules for every layerLayout, sign-off
DRC and LVS rule decksThe rules written as code for Calibre, IC Validator or PegasusPhysical verification before tape-out
RC extraction filesResistance and capacitance of each metal and via layerParasitic extraction, timing, signal integrity
Technology filesLayer definitions and display settings for layout editorsLayout editing
IP validation dataSilicon results for memory compilers, I/O and analog blocksIntegration and IP sign-off

Lock-in

A Design Built on One Kit Cannot Move to Another Foundry

Every part of a kit is calibrated to one foundry's process, so the foundry choice comes before almost every other design decision. A chip built for TSMC N3 cannot move to Samsung SF3 or Intel 18A without new device models, new cells, new rules and requalified IP: in practice a redesign that costs years and tens of millions of dollars. Customers that build a family of products on one foundry's kits tend to stay for the next node. The kits are one reason TSMC held 72.5% of foundry revenue in the second quarter of 2026 (TrendForce), and the main reason second-source plans for leading-edge chips rarely happen.

Ecosystems

Each Foundry Certifies Its Own Tools and IP

Foundry design ecosystems
FoundryProgramWhat it certifiesNote
TSMCOpen Innovation Platform (OIP)EDA Alliance, IP Alliance, Design Center Alliance, Cloud Alliance, Value Chain Alliance, 3DFabric AllianceThe 18th OIP forum in September 2026 covered N2, A16 and A14 flows
Samsung FoundrySAFE (Samsung Advanced Foundry Ecosystem)EDA, IP, design services, cloud, packaging partnersSF2 kits for gate-all-around nodes
Intel FoundryIntel Foundry Accelerator ecosystemEDA reference flows and IP for 18A, 18A-P and 18A-PTEarly 14A kit delivered to lead customers
GlobalFoundriesEcosystem partner programEDA and IP for 22FDX, 12LP+ and RF processesNow also owns MIPS and ARC processor IP
SMIC and Hua HongDomestic design service and IP partnersKits for 28nm and above, plus SMIC's 7nm-class N+2 for selected customersChinese EDA certified at mature nodes

Leading-edge kits

Gate-All-Around Kits From Three Foundries

Leading-edge kits, October 2026
NodeFoundryTransistorStatus
N2TSMCGate-all-around nanosheetIn volume production since the fourth quarter of 2025
A16TSMCNanosheet with Super Power Rail backside powerVolume production scheduled for the second half of 2026
A14TSMCSecond-generation nanosheetPlanned for 2028; design flows shown at OIP 2026
18AIntelRibbonFET with PowerVia backside powerIn production for Intel products; offered to foundry customers
14AIntelRibbonFET 2 with PowerDirectEarly kit with lead customers
SF2SamsungMulti-bridge channel FET (gate-all-around)Ramping; Tesla AI5 and other customers reported

Open PDKs

Open Kits Stop at 130 and 180 Nanometers

A handful of kits are open to anyone. Google and SkyWater released the SKY130 kit for SkyWater's 130nm process in 2020, followed by GlobalFoundries GF180MCU and the IHP SG13G2 130nm silicon-germanium process in Germany. They are used for teaching, research and low-volume chips through shuttle programs that put many designs on one wafer. Efabless, which ran the main shuttle service, closed in March 2025 and cancelled runs covering about 500 designs; ChipFoundry, started by its founders, took over SKY130 shuttles at about $15,000 for 100 chips, up from $10,000. Open kits stop far short of the leading edge, where no foundry publishes its rules.

China

Chinese Designers Are Cut Off From Leading-Edge Kits

Chinese designers lose access to leading-edge kits in three ways: Entity List designations, TSMC's late-2024 halt on shipping 7nm-and-below AI chips to Chinese customers, and the 2025 due diligence rule. Domestic foundries fill part of the gap. SMIC offers kits at 28nm and above to most customers and its 7nm-class process to selected ones such as Huawei's HiSilicon, and Hua Hong covers specialty and mature nodes. Empyrean's tools have been certified on some mature-node foundry flows, which lets a Chinese design reach tape-out without US software at those nodes.

Record

Page Record

Covers
PDK access and the foundry due diligence rule, kit contents, foundry lock-in, foundry ecosystems, leading-edge kits, open PDKs and China
Sources
BIS interim final rule on foundry due diligence (January 16, 2025), Wilson Sonsini summary; TSMC OIP pages and 2026 OIP forum agenda via SemiWiki; Intel Foundry DAC 2026 ecosystem note via SemiWiki; TrendForce foundry ranking for the second quarter of 2026; eeNews Europe on Efabless and ChipFoundry (May 2025); Empyrean certification as reported in industry research
Last verified
October 2026