Leading-Edge Logic Fabs

Operators

Three Operators at Volume, Two Entrants

TSMC, Samsung Foundry and Intel run leading-edge logic at commercial volume. Rapidus in Japan is entering at 2nm, and SMIC in China reaches 5nm-class without EUV.

Through the 2000s IBM, Motorola, AMD, Texas Instruments and others ran their own advanced logic lines. Capital and process development costs, and the rise of the fabless-foundry model, narrowed the field to TSMC, Samsung, Intel and GlobalFoundries by the mid-2010s, and GlobalFoundries stopped leading-edge development at 7nm.

FinFET to gate-all-around

The Move From FinFET to Gate-All-Around

Gate-all-around (GAA) nanosheet transistors replace FinFETs at 2nm-class nodes. The gate wraps every side of each channel, which holds switching control at gate lengths a fin cannot.

• Samsung moved first, with GAA at 3nm (SF3) in 2022. Early yields slowed customer adoption but gave Samsung several generations of GAA learning.
• TSMC kept FinFET through N3 and N3E and introduced GAA at N2, ramping since late 2025. A16 adds backside power delivery.
• Intel introduced GAA as RibbonFET at 18A, together with PowerVia, the first backside power delivery in volume. Power wiring moves to the back of the wafer, freeing the front for signals.

EUV

EUV Is the Tool No Fab Can Substitute

ASML in Veldhoven, Netherlands is the only maker of extreme ultraviolet (EUV) scanners, and every leading-edge line outside China runs them. The supply behind each scanner is a chain of single sources: Carl Zeiss SMT optics, Trumpf CO2 drive lasers, the EUV light source from ASML's San Diego unit (formerly Cymer), Lasertec actinic mask inspection and Hoya mask blanks.

High-NA EUV raises the numerical aperture from 0.33 to 0.55 at about $350 million a tool. Intel's 14A is the first node designed around High-NA, developed at the D1X fab in Hillsboro, Oregon on the first commercial ASML EXE:5200B. TSMC plans A14 without High-NA. The tools are covered on ASML EUV Scanner.

Capital

Capital Intensity

With cost per transistor flat, a leading-edge node has to pay for itself in performance: AI accelerator throughput, phone battery life, server core count. That narrows the customer base to the companies that can monetize it.

AI demand

AI Accelerators Fill the Leading Edge

Through the 2010s Apple A-series and Qualcomm Snapdragon phone chips set the volume for each new TSMC node. Since about 2022 AI accelerators have joined them: NVIDIA Blackwell and Rubin, AMD Instinct, Google TPU, AWS Trainium, Microsoft Maia and Meta MTIA all run on TSMC. In 2Q 2026 TrendForce reported TSMC's 5nm, 4nm and 3nm capacity fully booked by AI server GPUs and custom accelerators.

• Bigger dies: flagship accelerator dies run near the 800 square millimeter reticle limit, so each chip takes more wafer area.
• Three linked constraints: each accelerator joins leading-edge logic with HBM in CoWoS packaging, so all three have to scale together.
• Higher wafer prices: a $25,000 to $40,000 accelerator carries far more wafer cost than a $20 to $60 phone chip.

Packaging capacity is on CoWoS and the chips on AI Accelerators.

Leading-edge fabs

Leading-Edge Fabs and US Production Status

Each row is a leading-edge fab from the SemiconductorX fab dataset, banded by whether it produces in the United States.

• Made in US
• Some US volume
• US planned
• Made abroad

Taiwan concentration

Taiwan Holds Most of the World's Leading-Edge Capacity

About 90% of sub-5nm logic is made in Taiwan, on SIA and BCG estimates, and a sustained loss of TSMC's Taiwan output would leave no short-term substitute: Samsung Korea and the US lines together run a small fraction of TSMC Taiwan's volume, and replacing it would take years. The usual framing is a cross-strait conflict, but an earthquake near Hsinchu, a grid failure or a drought produces the same supply loss.

The US build-out lowers that share without removing it. TSMC Arizona runs N4 now and adds N3 in 2027; Intel runs 18A in Arizona; Samsung Taylor is starting 2nm; Terafab, the SpaceX and Tesla fab broke ground in Grimes County, Texas in August 2026 with limited operations targeted for late 2027. Through the late 2020s Taiwan stays the largest leading-edge producer. Concentration detail is on the Bottleneck Atlas.

China without EUV

SMIC Reaches 5nm-Class Without EUV

US and Dutch export controls keep EUV scanners out of China, so SMIC builds its advanced nodes by multi-patterning with ASML deep ultraviolet (DUV) immersion tools. TechInsights confirmed in December 2025 that Huawei's Kirin 9030 is made on SMIC N+3, a scaled evolution of its 7nm-class N+2, and found it still significantly less dense than TSMC and Samsung 5nm.

Multi-patterning takes more passes per layer, so SMIC's yields and costs trail EUV fabs, but the output supplies Huawei phones and Ascend AI accelerators that US controls keep from buying at TSMC. SMIC's revenue grew 20% in 2Q 2026, moving it close to Samsung for second place in foundry revenue. China's wider position is on the China Bifurcation spotlight.

Intel and Rapidus

Intel 14A and Rapidus 2nm Decide Whether the Field Widens

• Intel 14A: prospective foundry customers make supplier decisions from the second half of 2026 into early 2027. The 14A process design kit reaches customers in October 2026, two customers are evaluating test chips, and Musk said in April 2026 that Terafab will use 14A. Ohio One, designated for 14A, now opens its first module in 2030 to 2031, and Intel cancelled Magdeburg, Germany in July 2025.
• Rapidus: the IIM-1 pilot line in Chitose produced 2nm gate-all-around prototypes with the expected electrical characteristics in July 2026. Volume is planned for the second half of fiscal 2027 at about 6,000 wafers a month, rising to about 25,000. No high-volume customer has signed; Tenstorrent and Esperanto hold design partnerships.

Related coverage

Related Coverage

• Mature Logic Fabs
• DRAM Fabs
• TSMC
• Intel Foundry
• ASML EUV Scanner
• US Reshoring
• Samsung Taylor on AustinIO