Semiconductor Industry Glossary

This analyst-level glossary collects key terms, acronyms, and concepts used across SemiconductorX, focusing on fabrication, lithography, packaging, chip types, equipment, materials, supply chain, and sovereignty.

200mm wafer: A silicon wafer with 200 millimeter diameter, standard for mature-node (≥65nm) manufacturing. Still dominant for power, analog, and legacy logic production. Supply tightness is a recurring concern given limited global 200mm capacity.
300mm wafer: A silicon wafer with 300 millimeter diameter, standard for leading-edge and advanced-node logic, DRAM, and NAND production. Offers higher die yield per wafer but requires different equipment than 200mm lines.
450mm wafer: A proposed larger wafer standard never commercialized despite industry consortium efforts in the 2010s. Equipment cost economics and tooling reuse concerns halted transition.
3DIC: Three-dimensional integrated circuit. Multiple active silicon dies stacked vertically with through-silicon vias providing inter-die electrical connection. Enables higher density and shorter signal paths vs. planar multi-chip modules.
5G RF front end: The analog and RF components handling wireless signal transmission and reception in 5G devices, typically including power amplifiers, low-noise amplifiers, filters, and switches. Often uses GaAs or GaN technology.
ABF — Ajinomoto Build-up Film: A dielectric laminate film used in advanced IC substrate manufacturing, produced essentially exclusively by Ajinomoto Fine-Techno. Critical chokepoint for advanced packaging; supply constraints directly limit CoWoS and HBM production.
AEC-Q100: Automotive Electronics Council qualification standard for integrated circuits in automotive applications. Defines stress-test methods (temperature cycling, humidity, mechanical stress, electrical overstress) that parts must pass to be marketed as automotive-grade. AEC-Q101 covers discretes; AEC-Q200 covers passives.
Advanced packaging: Packaging technologies beyond traditional wire-bond and flip-chip, including 2.5D interposer-based integration (CoWoS, EMIB), 3D stacking with through-silicon vias, fan-out wafer-level packaging, and hybrid bonding. Critical for AI accelerators and HBM integration.
AI accelerator: A specialized integrated circuit designed to efficiently execute AI training or inference workloads. Categories include GPUs (NVIDIA, AMD), TPUs (Google), custom ASICs (AWS Trainium/Inferentia, Microsoft Maia, Tesla Dojo D1, Cerebras, Groq), and NPUs (mobile and edge).
AI Factory: A data center purpose-built for AI training or large-scale inference, typically featuring exceptional GPU/accelerator density, liquid cooling, high-bandwidth interconnect fabrics, and multi-hundred-megawatt power capacity. Examples include xAI Colossus, Tesla Cortex, Stargate.
AI5 / AI6 / AI7: Tesla's planned generations of custom AI inference chips. AI5 is scheduled for external fabrication (Samsung Taylor and TSMC Arizona). AI6 and AI7 are planned for Tesla's own Terafab. AI7 is designed as radiation-tolerant (not fully rad-hard) with LEO satellite applications.
Analog IC: An integrated circuit that processes continuous signals rather than discrete digital values. Includes op-amps, ADCs, DACs, voltage references, amplifiers, and signal conditioning circuits. Distinct from digital logic in design methodology and process requirements.
Anneal: A thermal process step that activates implanted dopants and repairs crystal lattice damage. Typically performed via rapid thermal processing (RTP), furnace anneal, or laser anneal depending on thermal budget requirements.
ArF immersion lithography: 193nm argon-fluoride excimer laser lithography with a water immersion layer between lens and wafer, improving resolution beyond dry ArF. Dominant technology for nodes above ~7nm before EUV. ASML, Nikon, and Canon produce immersion scanners.
ASIC — Application-Specific Integrated Circuit: An integrated circuit designed for a particular end application rather than general-purpose use. Examples include AWS Trainium, Google TPU, Tesla D1, Bitcoin mining chips. Offers better performance and efficiency than general-purpose alternatives for the target workload.
ASML: Dutch company manufacturing photolithography systems, including the only production-available EUV lithography equipment globally. Single-source supplier for EUV creates a structural supply chain chokepoint.
Atomic Layer Deposition (ALD): A thin-film deposition technique delivering one atomic or molecular layer per cycle through sequential self-limiting surface reactions. Essential for high-k dielectrics, conformal films on 3D structures, and advanced-node gate stacks.
Back-end of line (BEOL): The manufacturing steps following active device formation, creating metal interconnects that wire transistors together. Typically involves 10-15+ metal layers of copper (damascene) or aluminum (legacy) with interlayer dielectrics. Distinguishes from FEOL.
Back-end of semiconductor manufacturing: Assembly, packaging, and test operations that transform finished wafers into packaged chips ready for integration into systems. Distinct from front-end (wafer fabrication). Heavily concentrated in Taiwan, Malaysia, Vietnam, China, Korea.
BCD — Bipolar-CMOS-DMOS: A mixed-signal process technology combining bipolar, CMOS, and DMOS transistors on a single die, enabling integrated power management ICs. Common for PMICs, motor drivers, and automotive power devices.
Besi — BE Semiconductor Industries: Dutch company manufacturing die-attach, packaging, and advanced hybrid-bonding equipment. Market leader in hybrid bonding tooling, which is critical for advanced 3D stacking.
BGA — Ball Grid Array: A package type where interconnect is made via an array of solder balls on the package underside. Widely used for high-pin-count logic ICs. Distinguished from LGA (lands instead of balls).
Bipolar transistor: A three-terminal transistor using both electron and hole current flow, distinct from field-effect (MOS) transistors. Common in high-speed analog, RF, and some power applications. BiCMOS and BCD processes integrate bipolar with CMOS.
Black silicon: Wafers that cannot pass qualification testing due to defects, yield issues, or process excursions. Scrapped material representing lost value.
Bottleneck Atlas: SemiconductorX's flagship analytical reference mapping the 13 most concentrated chokepoints in global semiconductor production, ranked by cross-infrastructure criticality. Covers EUV, CoWoS, HBM, leading-edge foundries, SiC boule growth, photoresist, and other structural constraints.
Boule: A cylindrical single-crystal ingot of semiconductor material, sliced into wafers for subsequent fabrication. Silicon boules are produced via Czochralski or float-zone processes; SiC boules use physical vapor transport over days.
CAGR — Compound Annual Growth Rate: The annualized growth rate of a metric over a multi-year period. Commonly cited for semiconductor market growth, fab capacity additions, or chip category expansion.
Capex: Capital expenditure. For semiconductor manufacturing, typically dominated by equipment purchases; a leading-edge 300mm logic fab requires $15-25 billion in capex. TSMC, Samsung, Intel, and SMIC each spend tens of billions annually.
Cassette: A wafer-handling container holding 13-25 wafers in standardized slots. Most modern fabs use FOUPs (Front Opening Unified Pods) for 300mm wafers in contamination-controlled environments.
CC EAL — Common Criteria Evaluation Assurance Level: International security certification scheme (ISO/IEC 15408) for IT products. Levels EAL1 through EAL7 denote increasing rigor. EAL4+ and EAL5+ are commonly required for secure elements, smart cards, and government security modules.
CCM — Critical Component Manufacturing: Designations under CHIPS Act and similar programs for facilities producing components deemed nationally strategic.
Chemical-Mechanical Planarization (CMP): A process that removes material and planarizes wafer surfaces via simultaneous chemical etching and mechanical polishing. Required for damascene copper interconnect, STI, and other flat-topography requirements. Consumables (slurries, pads) are supply chain concentration points.
CHIPS Act: The CHIPS and Science Act of 2022, a US federal law providing approximately $52 billion in semiconductor manufacturing subsidies plus $13 billion for R&D, workforce, and related programs. Section 103 establishes domestic content requirements; Treasury FEOC rules restrict foreign-entity-of-concern participation.
Chiplet: A small, modular integrated circuit designed to be combined with other chiplets via advanced packaging to form a complete system. Enables mixing process nodes (e.g., compute on 3nm, I/O on 7nm) and reusing validated IP. AMD, Intel, Apple, and others use chiplet architectures.
CIS — CMOS Image Sensor: An integrated circuit using CMOS process to convert light into electrical signals. Dominant technology in smartphones, automotive, and industrial imaging. Sony is the dominant global producer; Samsung and OmniVision are major players.
CMOS: Complementary Metal-Oxide-Semiconductor. A transistor architecture using both NMOS and PMOS devices for low static power consumption. Dominant for digital logic since the 1980s.
Cleanroom: A manufacturing environment with strict controls on airborne particulates, temperature, humidity, and vibration. Semiconductor fabs operate at Class 1-100 (ISO 3-5), with stricter standards required for smaller nodes. Full fab buildout includes complex HVAC, particulate filtration, and vibration isolation.
CMP slurry: A liquid suspension containing abrasive particles and chemical reagents used in chemical-mechanical planarization. Specific formulations exist for tungsten, copper, oxide, and barrier-metal CMP. Supply concentrated among a few vendors (Cabot, Versum/Merck, Fujimi).
Concentration test: SemiconductorX's analytical discipline for evaluating claims of supply chain chokepoints. Tests whether a claimed bottleneck is actually concentrated (single-source or near-single-source), genuinely critical (disruption cascades), and structurally difficult to substitute, rather than merely editorially convenient to call a chokepoint.
Copper interconnect: The use of copper rather than aluminum for wafer-level wiring, transitioned industry-wide starting in the late 1990s. Requires damascene processing and barrier metal liners due to copper's diffusion behavior.
CoWoS — Chip on Wafer on Substrate: TSMC's advanced packaging technology integrating logic dies with HBM memory via a silicon interposer. Essential for NVIDIA H100/H200/B200 and similar AI accelerators. Supply is structurally constrained; CoWoS capacity is one of the tightest chokepoints in the AI accelerator supply chain.
Crystal growth: The formation of single-crystal semiconductor ingots from a melt or vapor. Silicon uses Czochralski; SiC uses physical vapor transport; GaN, GaAs, and specialty materials use epitaxy or other techniques.
Cu pillar: Copper interconnect columns replacing traditional solder bumps in advanced flip-chip assembly. Enables finer pitch and higher current density than solder-bump interconnect.
Czochralski process (CZ): The dominant silicon boule growth process, pulling a rotating single-crystal seed from molten silicon to form a cylindrical ingot. Produces most 200mm and 300mm wafers. Contrast with float-zone for ultra-pure applications.
Damascene: A metal-interconnect patterning process where dielectric is patterned, metal deposited, and excess metal removed by CMP. Dual-damascene forms vias and trenches in one sequence. Standard for copper interconnect at advanced nodes.
DDR — Double Data Rate: A class of synchronous DRAM memory transferring data on both clock edges. Generations include DDR4, DDR5, LPDDR5 (low-power), and GDDR6/GDDR7 (graphics). Distinct from HBM which uses stacked architecture.
DFARS Trusted Foundry: US Department of Defense Federal Acquisition Regulation Supplement accreditation for foundries producing secure, trusted semiconductor components for military and intelligence applications. GlobalFoundries (originally IBM Microelectronics) historically held primary Trusted Foundry status.
Die: An individual integrated circuit cut from a processed wafer. Synonymous with "chip" in some contexts. Die size, yield, and defect density are fundamental economic parameters.
DIMM — Dual In-line Memory Module: A memory module format containing multiple DRAM chips on a PCB with a standardized connector for server and desktop memory. Variants include RDIMM (registered), LRDIMM (load-reduced), and UDIMM (unbuffered).
Discrete: A single-function semiconductor device (transistor, diode, rectifier) rather than an integrated circuit. Power discretes include MOSFETs, IGBTs, SiC MOSFETs, and GaN HEMTs.
DRAM — Dynamic Random Access Memory: Volatile semiconductor memory requiring periodic refresh, dominant for main memory in computers and servers. Global production is concentrated among Samsung, SK Hynix, and Micron. Generations include DDR4, DDR5, LPDDR, and HBM.
DSMC — Defense and Semiconductor Manufacturing Capability: Generic framing for fab capacity classified as serving defense-critical applications.
DUV — Deep Ultraviolet lithography: Photolithography using 248nm (KrF) or 193nm (ArF) wavelengths. ArF immersion was the workhorse for advanced logic before EUV adoption. ASML, Nikon, and Canon produce DUV equipment.
EDA — Electronic Design Automation: Software tools for integrated circuit design, verification, simulation, and layout. Dominated by Synopsys, Cadence, and Siemens EDA (formerly Mentor Graphics). Represents a distinct supply chain chokepoint with implications for Chinese access restrictions.
Edge AI: AI inference executed at or near the data source rather than in centralized cloud. Requires specialized hardware (NPUs, edge accelerators) optimized for low power, low latency, and physical deployment constraints.
Entity List: A US Department of Commerce list of foreign persons and entities subject to export license requirements. Semiconductor-related Entity List additions have restricted SMIC, YMTC, CXMT, Huawei HiSilicon, and numerous Chinese companies from accessing US-origin technology.
Epitaxy (epi): A thin-film growth process where deposited material adopts the crystal structure of the substrate. Required for HBT, SiGe, SiC power devices, GaN devices, and various advanced CMOS elements.
EPC — Export Processing Controls: Generic framing for export control regulations governing semiconductor exports. US implementations include EAR (Export Administration Regulations), ITAR for defense items, and FDPR (Foreign Direct Product Rule) for foreign-produced items incorporating US technology.
ESD — Electrostatic Discharge: A sudden flow of electricity between two charged objects. Semiconductor devices require ESD protection structures (diodes, clamps) to prevent gate-oxide damage during handling and operation.
Etch: A process step removing material via chemical (wet etch) or plasma (dry etch / reactive ion etch) means. Modern advanced-node etching uses atomic layer etching (ALE) for extreme precision. Lam Research, Applied Materials, and TEL are major etch equipment suppliers.
EUV — Extreme Ultraviolet lithography: Photolithography using 13.5nm wavelength light, enabling patterning below ~7nm nodes. Only ASML produces production EUV systems; the ecosystem includes Zeiss optics, Trumpf laser source, Cymer light source, Mitsui pellicles, and Hoya/AGC mask blanks. Structural single-point chokepoint.
EUV photoresist: Photosensitive polymer formulated specifically for 13.5nm EUV exposure. Supply is concentrated among Japanese chemical companies (JSR, Tokyo Ohka Kogyo, Shin-Etsu, Fujifilm), representing a separate chokepoint within the EUV ecosystem.
Fab: A semiconductor fabrication facility. Modern 300mm leading-edge fabs cost $15-25 billion and require years to build. Naming conventions vary: "Fab 18" (TSMC Tainan), "Line 17" (Samsung), "Fab 42" (Intel Arizona).
Fab construction cluster: The concentration of specialized fab construction capability among a small number of firms (Fluor, Bechtel, Exyte, Mace), creating a downstream constraint on how fast CHIPS Act and foreign fab buildouts can proceed.
Fabless: A semiconductor company that designs chips but outsources fabrication to foundries. NVIDIA, AMD, Qualcomm, Apple, Broadcom, and MediaTek are major fabless companies. Contrasts with IDM (integrated device manufacturer) and pure-play foundry.
FEOL — Front-end of line: The manufacturing steps that form active transistor structures on the wafer, including well formation, gate structures, source/drain, and silicidation. Precedes BEOL interconnect formation.
FEOC — Foreign Entity of Concern: US Treasury Department designation for foreign entities whose participation in subsidized manufacturing is restricted under CHIPS Act rules. Implementation targets PRC, Russia, Iran, and North Korea entities.
FinFET: A non-planar transistor architecture using vertical fin structures for the channel, adopted at 22nm/16nm nodes to improve electrostatic control vs. planar. Dominant logic transistor architecture from ~2012 until GAA adoption at 3nm/2nm.
FIPS 140-3: US federal standard (FIPS 140-3) specifying security requirements for cryptographic modules. Required for US government procurement; levels 1-4 denote increasing rigor. Commonly applied to HSMs, TPMs, and security ICs.
Flip-chip: A packaging method that flips the die face-down and connects to the substrate via solder bumps or copper pillars rather than wire bonds. Enables higher pin counts and better electrical performance than wire-bond at cost of thermal and reliability complexity.
Float-zone (FZ): An alternative silicon boule growth process producing exceptionally pure crystals by passing a molten zone through a polysilicon rod. Used for power devices, detectors, and specialty applications requiring minimum oxygen and metallic contamination.
Foundry: A semiconductor manufacturer providing fabrication services to external fabless customers rather than selling own-designed chips. Pure-play foundries include TSMC, GlobalFoundries, UMC, and SMIC. Distinguished from IDMs (Samsung, Intel) which operate both foundry and own-product fabrication.
FOUP — Front Opening Unified Pod: A sealed plastic container holding 25 300mm wafers in contamination-controlled environment. Standard handoff interface between fab tools.
Front-end of semiconductor manufacturing: Wafer fabrication steps creating functional integrated circuits on the silicon substrate, prior to wafer dicing and packaging. Heavily concentrated at TSMC Taiwan, Samsung Korea, Intel US, SK Hynix Korea, and emerging locations.
GaAs — Gallium Arsenide: A compound semiconductor used for RF front-end components, power amplifiers, photonics, and some specialty applications. Lower bandgap than GaN; higher electron mobility than silicon.
GaN — Gallium Nitride: A wide-bandgap compound semiconductor used for power electronics (chargers, data center PSUs, EV onboard chargers) and RF applications. Higher switching frequencies and efficiency than silicon; competes with SiC at mid-voltage applications.
Gate-all-around (GAA): A transistor architecture where the gate surrounds the channel on all sides, providing superior electrostatic control vs. FinFET. Adopted at 3nm/2nm by Samsung and TSMC. Also called nanosheet or nanowire depending on channel geometry.
GDSII: Graphic Database System II, a binary file format for representing integrated circuit mask layout data. The standard handoff format between design and manufacturing.
Germanium (Ge): A critical material used in fiber optics, infrared optics, SiGe bipolar devices, and some specialty semiconductors. China dominates global refining; export controls have been a subject of trade policy action.
Globalfoundries: A US-headquartered pure-play foundry formed from AMD's manufacturing spinoff and subsequent acquisitions including IBM Microelectronics. Holds DFARS Trusted Foundry status and serves defense, automotive, and specialty markets. No longer pursues leading-edge logic.
Hard mask: A durable material layer used as an etching mask when photoresist alone is insufficient. Common hard masks include silicon nitride, silicon oxide, titanium nitride, and carbon-based materials.
HBM — High Bandwidth Memory: Stacked DRAM memory with through-silicon via interconnect, providing substantially higher bandwidth than DDR-class DRAM via parallel wide interface. Essential for AI accelerators. Production dominated by SK Hynix, Samsung, and Micron; supply structurally constrained through 2026-2027.
HEMT — High Electron Mobility Transistor: A compound-semiconductor transistor architecture used extensively for RF and high-frequency applications. GaN HEMTs are increasingly used in power electronics.
HSM — Hardware Security Module: A physical computing device safeguarding cryptographic keys and performing cryptographic operations within a protected boundary. Used for PKI, payment processing, database encryption. Typically certified to FIPS 140-2/3 or Common Criteria.
IC — Integrated Circuit: A semiconductor device containing multiple electronic components (transistors, resistors, capacitors) fabricated on a single die. Synonymous with "chip" in many contexts.
IDM — Integrated Device Manufacturer: A semiconductor company that designs, manufactures, and sells its own chips rather than outsourcing fabrication. Intel, Samsung, TI, STMicroelectronics, Infineon are major IDMs. Distinguished from fabless+foundry model.
IEC 60601: International standard for medical electrical equipment safety and essential performance. Required for medical device semiconductor content; specific collateral standards address different device categories.
IEC 61508: International functional safety standard for electrical/electronic/programmable electronic safety-related systems. Foundation standard from which industry-specific derivatives (ISO 26262 for automotive, IEC 62061 for machinery) descend.
IGBT — Insulated Gate Bipolar Transistor: A power semiconductor combining MOSFET gate control with bipolar output characteristics. Dominant for high-voltage, high-current switching in industrial drives, traction, and grid applications. Being displaced by SiC MOSFETs at some voltage ranges.
IMS — Insulated Metal Substrate: A PCB substrate technology using a metal base (typically aluminum) with dielectric insulation, providing superior thermal conductivity. Common for LED modules and some power applications.
Industrial Triad: SemiconductorX's framing for the convergence of semiconductors (SX), electrification (EX), and datacenters (DX) at industrial scale — the three physical-infrastructure domains that enable the AI-industrial complex. Austin is the canonical single-location convergence example.
Ion implantation: A wafer fabrication step introducing dopant atoms (boron, phosphorus, arsenic, etc.) into silicon via ion beam acceleration. Controls device threshold voltages, source/drain formation, and well structures. Applied Materials and Axcelis are major equipment suppliers.
ISO/SAE 21434: International standard for automotive cybersecurity engineering. Addresses cybersecurity risk management across the vehicle lifecycle; required for UN Regulation 155 type approval.
ISO 26262: International functional safety standard for road vehicles, derived from IEC 61508. Defines ASIL (Automotive Safety Integrity Level) A through D; D is most stringent. Required for safety-critical automotive semiconductor content.
ITAR — International Traffic in Arms Regulations: US regulations controlling export of defense articles and services on the US Munitions List. Rad-hard semiconductors, certain specialty chips, and related technology may be ITAR-controlled.
KLA: US-headquartered equipment maker producing process control, metrology, and inspection systems essential for advanced-node fabrication. Dominates high-end wafer inspection market. Subject to US export restrictions affecting Chinese advanced fab buildouts.
KrF lithography: 248nm krypton-fluoride excimer laser lithography, used for nodes from ~350nm down to ~130nm. Superseded by ArF for advanced nodes but remains in use for some process layers.
Lead frame: A metal framework supporting a chip die during packaging and providing external electrical connections. Common in traditional dual-inline, small-outline, and quad-flat-package formats.
Leading-edge node: The most advanced semiconductor process technology available at a given time. As of mid-2026, 3nm is in volume production (TSMC N3, Samsung 3GAP) with 2nm ramping. Contrast with mature-node (≥65nm) and advanced-node (3nm-14nm).
LFP — Lithium Iron Phosphate: A lithium-ion battery cathode chemistry (referenced for context, not a semiconductor term per se but frequent in cross-network discussion). BYD and CATL dominate LFP production.
LiDAR ASIC: A specialized integrated circuit processing LiDAR signal acquisition and processing. Used in autonomous vehicle sensor systems.
Lithography: The process of patterning wafer surfaces via selective exposure of photoresist to UV light through a mask, defining device features. The technology defining node capability. Includes KrF (248nm), ArF (193nm), ArF immersion, EUV (13.5nm), and emerging high-NA EUV.
Litho stepper / scanner: Lithography exposure tools that expose one die field at a time (stepper) or scan slit-shaped exposure across the field (scanner). Modern advanced-node tools are scanners. ASML, Nikon, Canon are global suppliers.
LLM accelerator: A semiconductor device optimized for large language model training or inference workloads. Category includes NVIDIA H100/B200, Google TPU v5/v6, AWS Trainium 2, Cerebras CS-3, Groq LPU, Tenstorrent, SambaNova. Distinct from general AI accelerators in optimization focus.
Mask — Photomask / Reticle: A glass plate with patterned chromium used to project circuit patterns onto wafer photoresist during lithography. EUV masks use multilayer reflective blanks (Hoya, AGC). Mask set for leading-edge logic costs $5-30 million.
Mature-node: Semiconductor processes at 65nm and older (28nm, 40nm, 90nm, 0.13μm, etc.). Used for analog, power, automotive, industrial, and consumer MCUs. China is aggressively expanding mature-node capacity; supply dynamics differ substantially from leading-edge.
MCU — Microcontroller Unit: A small integrated circuit combining CPU, memory, and peripherals for embedded control applications. Mature-node MCU supply was a major chokepoint during 2020-2022; qualification lock-in for automotive MCUs creates multi-year switching costs even when capacity is available.
Metal gate / high-k: The transition from polysilicon gate + silicon oxide to metal gate + high-k dielectric (typically hafnium-based), adopted at ~45nm to manage gate leakage. Enabled continued scaling past classical scaling limits.
Metrology: Measurement of wafer parameters (film thickness, critical dimension, overlay, defects) during fabrication. KLA dominates high-end metrology. Concentration is structurally important — metrology/inspection chokepoints indirectly constrain advanced fab throughput.
MIL-PRF-38535 QML: US military performance specification defining qualification manufacturing line requirements for space, military, and high-reliability integrated circuits. QML-V and QML-Q denote different mission profiles.
MLCC — Multilayer Ceramic Capacitor: A passive component using alternating ceramic dielectric and metal electrode layers. Despite being passive, MLCC supply tightness directly affects semiconductor-product availability; Murata, Samsung Electro-Mechanics, and TDK dominate.
MOCVD — Metal-Organic Chemical Vapor Deposition: A crystal growth technique using metalorganic precursors, used for GaN, GaAs, and other compound semiconductor epitaxy. Aixtron and Veeco are major equipment suppliers.
MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor. The dominant transistor type for digital logic (NMOS, PMOS, CMOS) and many power applications. Silicon MOSFETs serve voltage ranges up to several hundred volts; SiC and GaN extend the range.
NAND flash: Non-volatile semiconductor memory using floating-gate or charge-trap structures organized in NAND logic arrays. Dominant for SSDs and storage. Major producers: Samsung, SK Hynix (including Solidigm), Micron, Kioxia/Western Digital, YMTC. 3D NAND (stacked) is current architecture.
Nanosheet: The specific gate-all-around transistor geometry using stacked horizontal semiconductor sheets as channels. TSMC N2, Samsung 3GAP, Intel 18A, Rapidus 2nm use nanosheet transistors.
NF3 — Nitrogen Trifluoride: A specialty gas used for cleaning deposition chambers in semiconductor and display manufacturing. Also a potent greenhouse gas subject to emissions monitoring under CEMS programs.
NMC — Nickel Manganese Cobalt: A lithium-ion cathode chemistry family (referenced for EX cross-network context).
Node: Semiconductor process generation identifier, historically tied to transistor gate length but now marketing-oriented. Advanced nodes (3nm, 5nm, 7nm) use specific foundry process names (e.g., TSMC N3E, Samsung 5LPE). Node names are not directly comparable across foundries.
OSAT — Outsourced Semiconductor Assembly and Test: Third-party providers performing packaging and test operations for fabless and IDM customers. ASE Technology, Amkor, JCET, Powertech, SPIL are major OSATs. Heavily concentrated in Taiwan, Malaysia, China.
Overlay: The alignment accuracy between successive lithographic patterns on a wafer. Critical for multi-pattern advanced-node manufacturing. Measured in nanometers.
Packaging: The process of encapsulating semiconductor dies into protective structures with electrical interfaces. Categories include wire-bond, flip-chip, BGA, QFN, wafer-level, and advanced packaging (CoWoS, fan-out, 3D stacked, hybrid bonding).
Packaging substrate: The laminate or silicon interposer providing electrical routing between die and board. Advanced packaging uses sophisticated substrates; ABF build-up substrates are a critical supply chain chokepoint.
Pellicle: A thin film protecting a photomask from particles during lithography. EUV pellicles are particularly challenging due to 13.5nm transmission requirements; Mitsui Chemicals is the dominant supplier.
PFC — Perfluorinated Compounds: A class of specialty gases used in semiconductor processing (etching, chamber cleaning). Potent greenhouse gases; semiconductor industry voluntary and mandatory emission reduction programs target PFCs.
Photoresist: A photosensitive polymer coating applied to wafers before lithography exposure, then selectively dissolved to create patterns. Formulated for specific wavelengths (KrF, ArF, ArF immersion, EUV). Japanese suppliers (JSR, Tokyo Ohka Kogyo, Shin-Etsu, Fujifilm, Sumitomo) dominate advanced photoresist.
PMIC — Power Management Integrated Circuit: A chip combining voltage regulators, charge controllers, sequencers, and related power functions. Ubiquitous in smartphones, laptops, data centers, automotive, and industrial systems.
Polysilicon: Polycrystalline silicon used both as electronic-grade material for wafer production and solar-grade material for PV cells. Hemlock, Wacker, and Chinese producers (GCL, Tongwei) are major suppliers.
PPA — Power, Performance, Area: The three primary metrics for semiconductor process and design optimization. Node generation improvements are commonly expressed as PPA gains (e.g., 30% faster at same power, 50% less power at same performance, or 40% area reduction).
Process Control: Cross-cutting fab discipline monitoring and adjusting process parameters in real-time to maintain yield and quality. Not a discrete process step but an ongoing capability integrating metrology, inspection, SPC, and advanced process control (APC).
Process node: See "Node" above.
Qualification-as-moat: SemiconductorX's analytical thesis that semiconductor qualification regimes (AEC-Q100, ISO 26262, MIL-PRF-38535 QML, FIPS 140-3, IEC 60601, etc.) function as structural competitive moats. Qualification costs and multi-year lock-in periods make already-qualified suppliers defensible even against lower-cost newcomers.
Rad-hard — Radiation-hardened: Semiconductor devices specifically designed and manufactured to withstand ionizing radiation for space, military, and nuclear applications. Contrasts with rad-tolerant (commercial parts selected for radiation environments) and commercial (no radiation considerations).
Rare earths: 17 chemically similar elements (15 lanthanides plus scandium and yttrium) used in magnets, catalysts, polishing compounds, and specialty electronics. China dominates global refining; export controls have been a recurring trade policy tool.
Reshoring: Relocation of manufacturing from offshore locations back to domestic ones. Semiconductor reshoring is a primary policy goal of CHIPS Act, EU Chips Act, and similar programs. Faces constraints from workforce, construction capacity, supply chain, and utility infrastructure.
Reticle: See "Mask" above. Often used interchangeably; "reticle" emphasizes the exposed-field nature (one die or set of dies per exposure).
RF — Radio Frequency: High-frequency electrical signals, typically MHz to tens of GHz. RF semiconductor content includes transceivers, power amplifiers, filters, and front-end modules. GaAs, GaN, and silicon RF-CMOS serve different RF application bands.
RoT — Root of Trust: Hardware-anchored security foundation providing cryptographic attestation, secure boot, and key storage. Commercial implementations include AWS Nitro, Google Titan, Microsoft Pluton, Apple Secure Enclave, various TPM modules.
RTP — Rapid Thermal Processing: A process step using short-duration high-temperature exposure (seconds) for dopant activation, silicidation, and film anneal. Alternative to furnace processing for thermal-budget-limited advanced nodes.
SAM — Serviceable Addressable Market: The portion of total addressable market that can be served by a specific company's products and go-to-market approach.
Samsung Foundry: The foundry business unit of Samsung Electronics, distinct from Samsung's memory business. Competes directly with TSMC at leading-edge nodes and is investing heavily in US capacity via Samsung Taylor.
Samsung Taylor: Samsung's advanced logic fab under construction/ramp in Taylor, Texas. Approximately $40 billion initial investment, with expansion to potentially $200 billion+ announced. Central to US reshoring narrative.
SCM — Storage Class Memory: A class of memory technologies positioned between DRAM (fast, volatile) and NAND (slower, non-volatile, capacity-oriented). Intel Optane was a commercial example; post-Optane SCM market remains limited.
SerDes — Serializer/Deserializer: A semiconductor block converting parallel data to serial high-speed transmission and back. Critical for chip-to-chip and chip-to-network interfaces in high-performance systems. Advanced node SerDes IP is a differentiation area.
Semi — SEMI (organization): The global semiconductor industry trade association, publishing industry standards (SEMI S2 for equipment safety, SEMI F47 for voltage sag tolerance, etc.) and running conferences (SEMICON West, SEMICON Taiwan).
Section 103 (CHIPS Act): The section of the CHIPS Act establishing domestic content requirements for US semiconductor investment tax credit eligibility. Affects equipment, materials, and construction sourcing decisions.
Security silicon: Semiconductor devices implementing security primitives: TPMs, HSMs, secure elements, roots of trust, IP for SoC integration. Market structurally concentrated; Infineon, NXP, STMicroelectronics, Microchip, Nuvoton are major players.
SiC — Silicon Carbide: A wide-bandgap compound semiconductor used extensively in power electronics above ~650V: EV traction inverters, fast chargers, industrial drives, solar inverters, data center power. Wolfspeed, STMicroelectronics, Infineon, onsemi, ROHM, II-VI dominate. Boule growth (physical vapor transport over days) is a primary chokepoint.
SiGe — Silicon Germanium: An alloy used in heterojunction bipolar transistors, strained-silicon CMOS channels, and some specialty applications. Enables higher performance than pure silicon in specific use cases.
Silicon wafer: The substrate on which integrated circuits are fabricated. Electronic-grade silicon wafers are produced by Shin-Etsu, SUMCO, Siltronic, GlobalWafers, and SK Siltron. Supply concentration in Japan (Shin-Etsu, SUMCO) is a structural concern.
SMIC — Semiconductor Manufacturing International Corporation: China's largest foundry, subject to US Entity List restrictions limiting advanced-node access. Produces at mature and advanced nodes within constraints of available equipment and IP.
SOC — State of Charge: Battery parameter (EX cross-network term).
SoC — System on Chip: An integrated circuit combining processor, memory, peripherals, and system functions on a single die. Common in mobile, automotive, and embedded applications. Apple A-series, Qualcomm Snapdragon, Tesla FSD are SoC examples.
Specialty gases: High-purity gases used in semiconductor processing: silane, ammonia, nitrogen trifluoride, hexafluorobutadiene, and many others. Air Liquide, Linde, Air Products, Mitsubishi Gas Chemical, Sumitomo Seika are major suppliers. Supply concentration and purity specifications create structural dependencies.
Sovereign silicon: Semiconductor production capacity considered strategically essential to national security and technological sovereignty. Basis for CHIPS Act, EU Chips Act, Korean K-Chips Act, and similar programs worldwide.
Sovereignty constraints: Limitations on domestic semiconductor buildout including grid interconnect, NEPA environmental review, workforce availability, water supply, transformer shortages, permitting delays, specialty materials import dependencies, and export control compliance burden. Covered in SemiconductorX's dedicated sovereignty constraints page.
SRAM — Static Random Access Memory: Semiconductor memory using bistable latching circuits (typically 6 transistors per bit) for fast, volatile storage. Used for CPU caches, buffers, and SRAM IP within SoCs. Scaling challenges at advanced nodes are a growing concern.
STI — Shallow Trench Isolation: The dominant technique for isolating adjacent transistors in CMOS processes, using etched trenches filled with dielectric. Replaces older LOCOS (local oxidation) approach.
Stockpile: Inventory held by customers or distributors as hedge against supply disruption. Automotive stockpile management became a major topic after 2020-2022 shortages.
Strained silicon: Silicon channel engineering using lattice mismatch (e.g., SiGe source/drain) to enhance carrier mobility. Used from ~90nm onward to extend performance scaling.
Substrate: In packaging context, the laminate or interposer providing routing between die and board. In wafer context, the underlying silicon or compound semiconductor wafer. Usage context clarifies meaning.
Subfab: The portion of fab infrastructure below the cleanroom containing gas delivery, chemical delivery, wastewater treatment, exhaust systems, and related support. Substantial portion of fab construction cost and complexity.
TAM — Total Addressable Market: The total market demand for a product category at full penetration. Commonly cited for semiconductor market sizing.
Taiwan concentration: The structural dependency of global advanced-node semiconductor production on Taiwan, particularly TSMC. Central geopolitical concern driving CHIPS Act and similar reshoring programs.
TEL — Tokyo Electron Limited: Japanese semiconductor equipment maker, major player in coater/developer (lithography track), etch, deposition, and cleaning tools. Central to global semiconductor equipment supply chain alongside Applied Materials, Lam Research, ASML, KLA.
Terafab: Tesla's planned ultra-large-scale semiconductor manufacturing facility, sized substantially beyond traditional fab scale. Research Terafab planned for Austin with production Terafab elsewhere in Texas. Targets Tesla's internal AI6/AI7 chip production.
Thermal budget: The cumulative temperature-time exposure a process flow can tolerate without degrading prior structures. Advanced nodes have increasingly constrained thermal budgets, driving RTP, laser anneal, and low-temperature process development.
Through-Silicon Via (TSV): Vertical electrical interconnect passing through a silicon die, enabling 3D stacking and 2.5D interposer integration. Critical for HBM, CoWoS, and advanced 3DIC implementations.
TPM — Trusted Platform Module: A hardware security component providing cryptographic services, platform attestation, and key storage per TCG specifications. Found in most modern PCs and servers; increasingly in embedded and industrial systems.
Trusted Foundry: DoD accreditation for facilities producing secure semiconductors for military and intelligence applications. GlobalFoundries historically holds primary accreditation.
TSMC: Taiwan Semiconductor Manufacturing Company, the world's largest and most advanced pure-play foundry. Produces approximately 90% of leading-edge logic globally. Central to Industrial Triad semiconductor layer; TSMC Arizona is the primary US reshoring investment.
Type approval: Regulatory certification that a product model meets applicable standards for sale in a given jurisdiction. Automotive semiconductor content requires type approval for the vehicles in which it's integrated.
Umicore: Belgian specialty materials company producing battery materials, catalysts, and semiconductor specialty chemicals. Precursor supplier for various semiconductor applications.
UMC — United Microelectronics Corporation: Taiwanese pure-play foundry focused on mature-node and specialty processes, distinct from TSMC's leading-edge focus.
UPW — Ultra-Pure Water: Water processed to extreme purity for semiconductor wafer cleaning and process chemistry dilution. Specifications include resistivity (18.2 MΩ·cm at 25°C), particle count, metallic ion content, organic content. UPW plants are substantial fab infrastructure investment.
US Outbound Investment EO: The 2023 US Executive Order establishing outbound investment restrictions in Chinese semiconductor, quantum, and AI sectors. Extends export control paradigm to US capital flows.
VIA (semiconductor context): A vertical electrical connection through a dielectric layer between metal interconnect levels. Distinguished from TSV which passes through the silicon substrate itself.
Wafer fab equipment (WFE): The capital equipment used in semiconductor wafer fabrication. Global WFE market is dominated by ASML, Applied Materials, Lam Research, TEL, and KLA.
Wafer starts per month (WSPM): Standard fab capacity metric measuring monthly wafer production. Leading-edge 300mm fabs typically target 50,000-100,000+ WSPM depending on process complexity.
Wide-bandgap semiconductor: Semiconductors with bandgap significantly larger than silicon (1.12 eV), including SiC (3.26 eV), GaN (3.4 eV), and diamond. Enable higher voltage, temperature, and frequency operation.
Wire bond: Traditional packaging interconnect using fine metal wires (gold, copper, aluminum) between die pads and package lead frames. Superseded by flip-chip for high-pin-count logic but remains dominant for cost-sensitive and mature applications.
Wolfspeed: US-headquartered SiC power semiconductor manufacturer, formerly Cree. Pioneer in SiC technology; operates Mohawk Valley Fab in New York and expanding US production.
Yield: The percentage of good die produced from a wafer or batch. Yield ramp is a primary determinant of fab economics; leading-edge node yields mature over 12-24 months from initial production.
YMTC — Yangtze Memory Technologies Corporation: Chinese 3D NAND producer, subject to US Entity List restrictions limiting advanced equipment access. Key player in Chinese memory self-sufficiency strategy.
Zeiss: German optical systems manufacturer, exclusive supplier of projection optics for ASML EUV lithography systems. Single-source position makes Zeiss a structural sub-chokepoint within the EUV ecosystem.