Semiconductor Glossary: Terms From Wafer to Package

0-9

2.5D packaging: Packaging that places several dies side by side on a silicon interposer or bridge so they can talk through fine wiring, as in CoWoS and EMIB. See page
200mm wafer: A silicon wafer 200 millimeters across, still the workhorse for power, analog, MEMS and other mature-node chips. See page
300mm wafer: A silicon wafer 300 millimeters across, the standard for leading-edge logic, DRAM and NAND, with about 2.25 times the area of a 200mm wafer. See page
3D IC: A chip built from dies stacked vertically and joined by through-silicon vias or hybrid bonds, giving short, dense links between layers. See page
3D NAND: Flash memory built as a vertical stack of hundreds of cell layers, with channel holes etched through the whole stack. See page
450mm wafer: A larger wafer size the industry studied in the 2010s and abandoned because new tools for it never paid back. See page

A

ABF (Ajinomoto Build-up Film): The insulating film used to build the wiring layers of advanced package substrates, made almost entirely by Ajinomoto in Japan. See page
Advanced packaging: Packaging that joins dies with dense interconnect (interposers, bridges, fan-out, die stacking or hybrid bonding) rather than a single die in a plain package. See page
AEC-Q100: The Automotive Electronics Council stress-test qualification that an integrated circuit must pass to be sold as automotive grade. See page
AI accelerator: A chip built to run AI training or inference, such as a GPU, TPU or custom ASIC. See page
AI5 and AI6: Tesla's in-house AI inference chips; AI5 is made at Samsung Taylor and TSMC, and AI6 is contracted to Samsung Taylor with TSMC Arizona as a second source. See page
ALD (atomic layer deposition): A deposition method that grows a film one atomic layer per cycle, giving even coverage on deep 3D shapes such as gate-all-around transistors. See page
ALE (atomic layer etch): An etch method that removes material one atomic layer per cycle for very fine control of depth and shape. See page
Analog IC: A chip that handles continuous signals, such as amplifiers, data converters and voltage references, rather than digital ones and zeros. See page
Anneal: A heating step that activates implanted dopants and repairs damage to the silicon crystal. See page
APC (advanced process control): Software that adjusts each tool's recipe run to run from measurement data to hold a process on target. See page
ArF immersion lithography: Deep ultraviolet lithography at 193nm with water between the lens and wafer, the main patterning method before EUV and still used on most layers. See page
ASIC (application-specific integrated circuit): A chip designed for one job, such as Google's TPU or AWS Trainium, rather than general-purpose use. See page
ASML: The Dutch company that is the only maker of EUV lithography scanners. See page
ATE (automated test equipment): The testers that drive electrical signals into a chip at wafer sort and final test and judge pass or fail. See page

B

Backgrinding: Grinding the back of a finished wafer to thin it before dicing, down to tens of microns for stacked memory. See page
Backside power delivery: Running a chip's power wires under the transistors on the back of the wafer, freeing the front-side wiring for signals, as in Intel PowerVia and TSMC Super Power Rail. See page
BCD (bipolar-CMOS-DMOS): A process that puts bipolar, CMOS and power DMOS transistors on one die, used for power management and motor driver chips. See page
BEOL (back-end-of-line): The fab steps that build the stack of metal wiring layers above the transistors. See page
Besi: The Dutch maker of die attach and hybrid bonding equipment that leads die-to-wafer hybrid bonding tools. See page
BGA (ball grid array): A package that connects to the board through an array of solder balls on its underside. See page
Big Fund: China's National Integrated Circuit Industry Investment Fund, which takes equity stakes in Chinese chip and equipment companies. See page
BIS (Bureau of Industry and Security): The US Commerce Department bureau that writes and enforces export controls on chips, tools and technology. See page
Bottleneck Atlas: SemiconductorX's map of the 18 chokepoints in the chip supply chain, who holds each and its US status. See page
Boule: A single-crystal ingot of silicon, silicon carbide or another semiconductor, later sliced into wafers. See page
Burn-in: Running chips hot and powered for hours to weed out early failures before they ship. See page

C

C4 bump: A solder bump that joins a flip-chip die or interposer to the package substrate. See page
Captive packaging: Assembly and test done in-house by a foundry or chipmaker rather than by an outside OSAT. See page
Chiplet: A small die designed to be combined with others in one package, letting each part use the best process node for its job. See page
CHIPS and Science Act: The 2022 US law that funds chip manufacturing grants, research programs and an investment tax credit for new fabs. See page
CIS (CMOS image sensor): A chip that turns light into electrical signals, used in phone, car and robot cameras. See page
Cleanroom: A fab space with filtered air and tight control of particles, temperature, humidity and vibration. See page
CMMC (Cybersecurity Maturity Model Certification): The US Defense Department's cybersecurity requirement for its contractors and suppliers. See page
CMOS: The complementary transistor design, pairing n-type and p-type devices, that nearly all digital logic uses. See page
CMP (chemical mechanical planarization): Polishing the wafer flat with a slurry and pad after deposition so the next layer can be patterned. See page
CMP slurry and pad: The abrasive liquid and polymer pad consumed in each CMP step, made by a short list of suppliers. See page
Co-packaged optics (CPO): Putting optical transceivers in the same package as a switch or processor to cut the power of electrical links. See page
Compound semiconductor: A semiconductor made of two or more elements, such as GaAs, InP, GaN or SiC, used for RF, optics and power. See page
CoWoS (Chip on Wafer on Substrate): TSMC's 2.5D packaging that places a GPU or ASIC beside HBM stacks on an interposer; the S, R and L versions use a silicon interposer, an organic interposer and silicon bridges. See page
Critical dimension (CD): The width of the smallest feature printed on a layer, measured to check that lithography and etch hit target. See page
Critical elements: Minor metals and gases such as gallium, germanium, antimony and helium that chips need in small amounts and few countries supply. See page
CVD (chemical vapor deposition): Depositing a film from gases that react on the wafer surface; PECVD uses a plasma to run it at lower temperature. See page
Czochralski process (CZ): Growing a silicon ingot by slowly pulling a rotating seed crystal from molten silicon; MCZ adds a magnetic field to calm the melt. See page

D

Damascene: Building copper wires by etching trenches into insulator, filling them with copper and polishing off the excess; dual damascene forms vias and wires together. See page
Dicing: Cutting a finished wafer into individual dies with a saw, laser or plasma. See page
Die: One chip cut from a wafer. See page
Die attach: Fixing a die to its package base or substrate with epoxy, solder or sintered silver. See page
Discrete: A single semiconductor device, such as a diode, MOSFET or IGBT, rather than an integrated circuit. See page
DRAM: Dynamic random access memory, the main working memory of computers, which must be refreshed constantly to hold data. See page
DUV (deep ultraviolet) lithography: Lithography with 248nm or 193nm light, used on most layers of every chip. See page

E

EDA (electronic design automation): The software used to design, simulate and verify chips, led by Synopsys, Cadence and Siemens. See page
EMIB (Embedded Multi-die Interconnect Bridge): Intel's 2.5D packaging that links dies through small silicon bridges set into the package substrate. See page
EMS (electronics manufacturing services): Contract manufacturers that build boards, servers and finished products from packaged chips. See page
Entity List: The US Commerce Department list of foreign companies that need a license to receive US-origin items, including many Chinese chipmakers. See page
Epitaxy (epi): Growing a thin crystal layer on a wafer that follows the wafer's crystal structure, used in power, RF and advanced logic devices. See page
Etch: Removing material through a patterned mask, with liquids (wet etch) or plasma (dry etch). See page
EUV (extreme ultraviolet) lithography: Lithography with 13.5nm light, needed to print the finest layers of leading-edge chips, with scanners made only by ASML. See page
EUV mask blank: The multilayer mirror plate on which an EUV photomask is written, made in volume only by AGC and Hoya. See page
Export controls: Government licensing rules on selling chips, tools, software and know-how abroad, such as the US Export Administration Regulations. See page

F

Fab: A wafer fabrication plant. See page
Fabless: A chip company that designs chips and pays foundries to make them, such as NVIDIA, AMD and Qualcomm. See page
Fan-out wafer-level packaging (FOWLP): Packaging that molds dies into a reconstituted wafer and builds wiring out past the die edge without a substrate. See page
FDPR (Foreign Direct Product Rule): A US export rule that reaches foreign-made items produced with US technology or tools. See page
FEOC (foreign entity of concern): A US legal category for companies tied to China, Russia, Iran or North Korea that limits their role in subsidized projects. See page
FEOL (front-end-of-line): The fab steps that build the transistors themselves, before the wiring layers. See page
Final test: Testing each packaged chip before it ships, often with burn-in and system-level test. See page
FinFET: A transistor whose channel is a thin vertical fin with the gate wrapped on three sides, used from about 22nm to 3nm. See page
Flip-chip: Mounting a die face down so bumps on its surface connect directly to the substrate. See page
Float zone (FZ): Growing very pure silicon by moving a molten zone along a rod, used for power devices and detectors. See page
Foundry: A company that makes chips designed by other companies, such as TSMC, Samsung Foundry and GlobalFoundries. See page
FOUP (front opening unified pod): The sealed carrier that holds 25 300mm wafers as robots move them between tools. See page
Foveros: Intel's 3D packaging that stacks logic dies face to face on a base die. See page
FPGA (field-programmable gate array): A chip whose logic can be rewired after manufacture. See page

G

GAA (gate-all-around): A transistor whose gate surrounds stacked silicon nanosheets on all sides, used from the 2nm generation. See page
GaAs (gallium arsenide): A compound semiconductor used for phone power amplifiers, RF switches and lasers. See page
GaN (gallium nitride): A wide-bandgap compound semiconductor used for fast, efficient power converters and high-power RF. See page
GDSII: The standard file format for a chip's finished layout, handed from design to the mask shop. See page
Germanium: A critical element used in SiGe transistors, infrared optics and fiber, refined mostly in China. See page
Glass substrate: A package substrate core made of glass instead of organic laminate, being developed for flatter, larger AI packages. See page
GPU (graphics processing unit): A chip with thousands of parallel cores, now the main engine of AI training. See page

H

HBM (high bandwidth memory): DRAM dies stacked on a base die and linked by through-silicon vias, placed beside an AI chip for very high bandwidth. See page
HBM4: The HBM generation with a 2048-bit interface and a logic base die, used in AI chips from 2026. See page
Helium: An inert gas used for cooling and leak checks in fabs, with a large share of world supply from Qatar. See page
HEMT (high electron mobility transistor): A transistor built in compound semiconductors such as GaN for high-frequency RF and fast power switching. See page
High-k metal gate: A gate stack that replaces silicon dioxide with a high-dielectric-constant insulator and a metal electrode to cut leakage. See page
High-NA EUV: ASML's EUV scanners with a 0.55 numerical aperture lens, able to print finer lines than standard 0.33 NA tools. See page
Hybrid bonding: Joining two dies or wafers by bonding copper pads and oxide directly, with no solder bumps, for pitches under 10 microns. See page

I

I-Cube: Samsung's 2.5D packaging that places logic and HBM on a silicon interposer. See page
IDM (integrated device manufacturer): A company that designs and makes its own chips, such as Intel, Texas Instruments and Infineon. See page
IGBT (insulated gate bipolar transistor): A high-voltage power switch used in motor drives, rail and grid equipment. See page
InFO (Integrated Fan-Out): TSMC's fan-out packaging, used for phone processors and in larger forms for AI chips. See page
InP (indium phosphide): A compound semiconductor used for the lasers and detectors in fiber-optic links. See page
Interposer: A thin silicon or organic layer that carries fine wiring between dies placed side by side on it. See page
Ion implantation: Firing dopant ions into the silicon at a set energy and dose to change its electrical properties. See page
IP core: A licensed, prebuilt design block, such as an Arm CPU or a memory interface, that chip designers drop into their chips. See page
ISO 26262: The functional safety standard for road vehicle electronics, with integrity levels ASIL A to D. See page
ITAR (International Traffic in Arms Regulations): US rules on exporting defense items, which cover some rad-hard and military chips. See page

J

JEDEC: The standards body that writes memory specifications such as DDR5 and HBM4. See page

K

KGD (known good die): A bare die tested well enough to be trusted before it goes into an expensive multi-die package. See page
KLA: The US company that leads wafer inspection and metrology equipment. See page

L

Lead frame: A stamped metal frame that holds a die and forms the leads of a traditional package. See page
Leading-edge node: The most advanced process in volume production at a given time, today the 3nm and 2nm class. See page
Lithography: Printing a circuit pattern onto photoresist on the wafer by shining light through a photomask. See page

M

Mature node: An older process, roughly 28nm and larger, used for analog, power, microcontrollers and most automotive chips. See page
MCU (microcontroller unit): A small chip that combines a processor, memory and peripherals to control a device. See page
MEMS (micro-electro-mechanical systems): Tiny mechanical structures made with chip processes, such as accelerometers, gyroscopes and microphones. See page
MES (manufacturing execution system): The fab software that tracks every wafer lot, tool and recipe through production. See page
Metallization: Depositing and patterning the metal contacts and wires that connect transistors. See page
Metrology: Measuring film thickness, line width, overlay and other properties on the wafer to keep processes on target. See page
Micro-bump: A small solder or copper bump, tens of microns across, that joins dies to an interposer or to each other. See page
MOCVD (metal-organic chemical vapor deposition): Epitaxial growth from metal-organic gases, used to grow GaN and other compound semiconductor layers. See page
Mold compound: The filled epoxy that encapsulates a chip to protect it inside its package. See page
MOSFET: The metal-oxide-semiconductor field-effect transistor, the basic switch of digital logic and power electronics. See page
MR-MUF (mass reflow molded underfill): SK hynix's method of bonding and filling all the dies in an HBM stack at once. See page

N

NAND flash: Non-volatile memory that keeps data without power, used in SSDs and phones. See page
Nanosheet: A thin horizontal silicon ribbon used as the channel of a gate-all-around transistor. See page
Neon: A gas used in the excimer lasers of DUV lithography. See page
NF3 (nitrogen trifluoride): A cleaning gas used to strip deposits from deposition chambers, and a strong greenhouse gas. See page
Node: A name for a process generation, such as 3nm or 2nm, that no longer matches any physical dimension on the chip. See page
Numerical aperture (NA): A measure of how much light a lens gathers; higher NA prints finer features. See page

O

OPC (optical proximity correction): Reshaping mask patterns so the printed features come out as designed despite optical distortion. See page
OSAT (outsourced semiconductor assembly and test): Companies such as ASE, Amkor and JCET that package and test chips for other companies. See page
Overlay: How precisely one patterned layer lines up with the layer beneath it. See page
Oxidation: Growing a silicon dioxide layer on the wafer by heating it in oxygen or steam. See page

P

Package substrate: The multilayer board inside a package that carries signals and power from the die to the solder balls. See page
Panel-level packaging: Building fan-out or other packages on large rectangular panels instead of round wafers to fit more packages per run. See page
PDK (process design kit): The foundry's files of rules, device models and libraries that designers need to design for one process. See page
Pellicle: A thin membrane stretched over a photomask to keep particles out of focus during exposure. See page
PFAS: Per- and polyfluoroalkyl substances, fluorinated chemicals used in fab materials that the EU and US are moving to restrict. See page
Photomask (reticle): A quartz plate carrying the pattern of one chip layer, used to expose the wafer in lithography. See page
Photoresist: The light-sensitive coating that records the lithography pattern so the layer below can be etched or implanted. See page
PMIC (power management IC): A chip that converts and regulates the voltages a system needs. See page
Polysilicon: Purified silicon, up to 11 nines pure for chips, melted to grow crystal ingots. See page
Probe card: The fixture of fine needles that touches every pad on a die so the tester can check it at wafer sort. See page
Process control: The measurement and software that keep each fab step on target and catch drift before it costs yield. See page
PVD (physical vapor deposition): Depositing metal films by sputtering atoms off a target onto the wafer. See page
PVT (physical vapor transport): Growing silicon carbide crystals by subliming SiC powder onto a seed at about 2,000 to 2,500 degrees Celsius. See page

Q

QML (Qualified Manufacturers List): The US Defense Department list of makers qualified to supply military and space grade microcircuits. See page

R

Rad-hard: Built to survive the radiation of space and nuclear environments, by design, process or both. See page
Rare earths: Elements used in magnets and some fab materials, mined and refined mostly in China. See page
Reshoring: Moving chip manufacturing back to the United States from abroad. See page
RF front end: The amplifiers, filters and switches between a phone's antenna and its modem. See page
RTP (rapid thermal processing): Heating single wafers for seconds with lamps or lasers for anneals and oxidation. See page

S

SAQP (self-aligned quadruple patterning): Using repeated deposition and etch to split one lithography pattern into four, printing lines finer than the scanner can alone. See page
Section 232: The US trade law that lets the president set tariffs or import limits on goods judged a national security risk, applied to chips and polysilicon. See page
SEMI: The global industry association for chip equipment and materials makers, which also writes the SEMI standards used in fabs. See page
SerDes (serializer/deserializer): A high-speed link block that sends parallel data over a few fast serial lanes. See page
SiC (silicon carbide): A wide-bandgap compound semiconductor used for efficient high-voltage power switches in EV inverters, chargers and grid gear. See page
SiGe (silicon germanium): A silicon process with germanium added for fast bipolar transistors in RF and high-speed circuits. See page
Silicon photonics: Building optical components such as modulators and waveguides on silicon wafers. See page
SiP (system in package): Several dies and passive parts combined in one package to form a whole subsystem. See page
Slicing: Cutting an ingot into wafers with a multi-wire saw. See page
Smart Cut: Soitec's method for making SOI wafers by splitting a thin silicon layer off a donor wafer with implanted hydrogen. See page
SoC (system on chip): One chip that combines CPU, GPU, AI engines, memory controllers and I/O. See page
SOI (silicon on insulator): A wafer with a thin silicon layer on a buried oxide, used for RF, photonics and low-power chips. See page
SoIC (System on Integrated Chips): TSMC's 3D stacking that joins dies with hybrid bonds. See page
SPC (statistical process control): Charting fab measurements against control limits to catch a drifting process. See page
Sputtering target: A plate of pure metal that PVD tools bombard to deposit thin metal films. See page
SRAM: Static random access memory, the fast on-chip cache memory built from six transistors per bit. See page
STI (shallow trench isolation): Oxide-filled trenches that electrically separate neighboring transistors. See page
Subfab: The floor below the cleanroom that holds the pumps, abatement, power and chemical supply for the tools above. See page
Supplier ring: SemiconductorX's map of every supplier behind one flagship chip, from logic die to memory, packaging and test. See page

T

TCB (thermocompression bonding): Bonding dies with heat and pressure one at a time, the main way HBM stacks are built today. See page
Terafab: The Tesla and SpaceX chipmaking program, with a research fab at Giga Texas and a volume fab planned in Grimes County, Texas. See page
Thermal budget: The total heat a wafer can take at a given stage before it damages structures already built. See page
TPU (tensor processing unit): Google's custom AI accelerator. See page
Trusted Foundry: A fab accredited by the US Defense Microelectronics Activity to make chips for defense programs. See page
TSMC: Taiwan Semiconductor Manufacturing Company, the largest foundry and the maker of nearly all leading-edge AI chips. See page
TSV (through-silicon via): A vertical copper connection through a silicon die, used in HBM stacks and 3D ICs. See page

U

UCIe (Universal Chiplet Interconnect Express): An open standard for links between chiplets in one package. See page
Underfill: Epoxy flowed under a flip-chip die to lock the bumps in place and spread stress. See page
UPW (ultrapure water): Water purified to parts-per-trillion contaminant levels for rinsing wafers. See page

W

Wafer fab equipment (WFE): The tools that process wafers in a fab: lithography, deposition, etch, implant, cleaning, CMP, thermal and metrology. See page
Wafer sort: Probing every die on a finished wafer to find the bad ones before packaging. See page
Wafer starts per month (WSPM): The usual measure of fab capacity: how many wafers a fab begins processing each month. See page
Wide-bandgap semiconductor: A material such as SiC or GaN whose wide bandgap lets devices handle higher voltage, heat and frequency than silicon. See page
Wire bonding: Connecting a die's pads to its package with fine gold, copper or aluminum wires. See page

Y

Yield: The share of dies on a wafer, or wafers in a lot, that work. See page

Z

Zeiss SMT: The German maker of the optics in ASML's lithography scanners, part-owned by ASML. See page