Fabless Design & IP Cores Overview

The fabless model separates chip design from manufacturing. Fabless companies develop architectures, integrate licensed IP, and generate mask-ready design files -- then outsource wafer fabrication to foundries and packaging to OSATs. This model has enabled explosive semiconductor innovation by lowering the capital barrier to chip development, but it has concentrated manufacturing at a handful of foundries (primarily TSMC) and created systemic dependencies on three software tools companies (Synopsys, Cadence, Siemens EDA) and one IP licensor (ARM) that together form the design infrastructure chokepoint of the global semiconductor supply chain.

Fabless Ecosystem

Segment	Representative Companies	Key Products	Foundry Dependency
GPUs & AI Accelerators	NVIDIA, AMD, Cerebras, Tenstorrent, Google TPU (captive design)	Training/inference accelerators, HPC GPUs, custom AI silicon	TSMC dominant for leading nodes; NVIDIA H100/H200/B200 all TSMC CoWoS
Mobile & Consumer SoCs	Qualcomm, MediaTek, Apple Silicon (design-only), Samsung LSI	Smartphone APs, modems, wearable chips	TSMC for Apple and Qualcomm flagship; Samsung for some MediaTek; heavy TSMC concentration
Networking & Datacenter	Broadcom, Marvell, Arista (custom ASICs), hyperscaler in-house (Google, Amazon, Microsoft)	Ethernet switch ASICs, SmartNICs, DPUs, custom AI inference chips	TSMC for leading-edge; TSMC 5nm/3nm for hyperscaler custom silicon
RF & Wireless	Qualcomm, Skyworks, Qorvo, Broadcom	5G modems, RF front-end modules, Wi-Fi/BT chips	Mix of TSMC, GlobalFoundries (RF-SOI), and compound semiconductor foundries
Automotive & ADAS	Mobileye, Qualcomm Automotive, NXP, Renesas (partly fabless)	ADAS SoCs, radar processors, EV control units	TSMC, Samsung; long qualification cycles reduce foundry switching flexibility
Specialized AI / Edge	Graphcore, Mythic, SiFive (RISC-V), Esperanto, Tenstorrent	Edge inference accelerators, RISC-V SoCs, domain-specific processors	TSMC and TSMC N7/N5 for leading-edge; some use GlobalFoundries or TSMC mature nodes

IP Core Categories

Category	Examples	Representative Vendors	Strategic Notes
CPU / GPU / DSP	ARM Cortex-A/M/R series; RISC-V cores; GPU IP; DSP cores	ARM (~41% semiconductor IP market share); SiFive, Andes (RISC-V); Imagination; Cadence Tensilica; CEVA	ARM near-monopoly in mobile and embedded; RISC-V growing as royalty-free alternative; see IP Licensing page
Interface & PHY	PCIe, CXL, DDR/LPDDR, HBM, USB, MIPI, SerDes, UCIe	Synopsys DesignWare (dominant); Cadence; Rambus; Alphawave	High-speed PHY IP is one of the most complex and highest-value IP categories; standard changes (PCIe 6, CXL 3, HBM4) require new IP qualification cycles
Security	Crypto engines, secure enclaves, PUF, key storage, secure boot, TEE	Rambus, Synopsys, Intrinsic ID (PUF), Arm TrustZone	Security IP export controls are a growing concern; PUF (physically unclonable function) technology is a growing segment for IoT and automotive
Analog & Mixed-Signal	PLLs, ADC/DAC, PMIC blocks, oscillators, bandgap references	Silicon Creations, Faraday, Synopsys, Cadence	Analog IP is highly process-specific -- a PLL qualified at TSMC N5 does not port directly to Samsung 4nm; foundry PDK dependency is strongest here
NoC & Cache Coherency	On-chip networks, AXI/CHI interconnect fabrics, cache coherency for multi-die	Arteris, ARM (CMN), SiFive	Growing demand from chiplet and multi-die architectures requiring die-to-die coherency management

Design Cost Economics

Advanced-node chip development costs have escalated to the point where they constrain who can participate in leading-edge design. A complete tape-out at 5nm (including EDA licenses, IP licensing fees, mask set costs, prototype runs, verification engineering, and NRE) can exceed $300-500 million. At 3nm, mask set costs alone run $10-20 million per design (see Photomasks page), and total tape-out costs approach $500 million or above for complex SoCs. These economics concentrate leading-edge design among a small number of companies with the revenue base to absorb NRE costs -- NVIDIA, Apple, Qualcomm, Broadcom, and hyperscaler custom silicon teams. They also make first-time silicon success critical: a tape-out respin at 3nm adds another $10-20M in mask costs and 6-12 months to the schedule.

Risks & Chokepoints

The design layer of the semiconductor supply chain has four structural chokepoints. First, foundry concentration: TSMC's ~67% share of pure-play foundry revenue means most leading-edge fabless designs are one TSMC disruption away from a production halt. Second, EDA concentration: Synopsys (~31%), Cadence (~30%), and Siemens EDA (~13%) collectively control approximately 75% of the global EDA market -- US export controls on EDA software to China, imposed and then partially lifted in 2025, demonstrated how this concentration can be weaponized. Third, ARM's near-monopoly in processor IP: ARM holds approximately 41% of the overall semiconductor IP market and an even larger share of mobile and embedded CPU IP. RISC-V is the primary alternative but is not yet competitive with ARM in performance-critical applications. Fourth, PDK lock-in: chips designed to a specific foundry's PDK cannot be ported to another foundry without a multi-year redesign effort.

Section Pages

IP Licensing | EDA Tools | PDK & Process Design Kits

Supply Chain Outlook

The fabless model continues to attract the majority of semiconductor innovation investment, but the economics of advanced-node design are bifurcating the industry: a small number of well-capitalized companies can afford leading-edge tape-outs, while the broader design community migrates to chiplet-based approaches (using pre-designed chiplets on advanced nodes, combined with custom logic on mature nodes) or to RISC-V custom cores that reduce per-unit royalty burden. The EDA export control episode of 2025 -- BIS directing Synopsys, Cadence, and Siemens to halt China sales before partially reversing -- confirmed that design software is now an active lever in the US-China tech competition, not merely a commercial product.

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