Fabless Chip Design

Design, licensed IP, rented EDA, bought wafers · NVIDIA, Broadcom, Qualcomm, AMD, MediaTek, HiSilicon

A fabless company designs and sells chips but owns no fab. The top 10 fabless companies earned more than $359.4 billion in 2025, and NVIDIA took $205.7 billion of it, 57%, more than the other nine combined. The six largest all build their main products at TSMC.

The top 10 fabless chip companies earned more than 359.4 billion dollars in 2025, up 44%. NVIDIA alone earned 205.7 billion dollars, 57% of the total, more than the next nine combined. Broadcom earned 39.7 billion, Qualcomm about 38.9 billion, AMD 34.6 billion and MediaTek 19.1 billion. TrendForce, April 2026. TOP 10 FABLESS COMPANIES, 2025 REVENUE, $B NVIDIA 205.7 Broadcom 39.7 Qualcomm 38.9 AMD 34.6 MediaTek 19.1 Marvell 8.0 Realtek 3.9 OmniVision 3.3 Novatek 3.2 MPS 2.8 SHARE OF THE TOP 10 TOTAL ($359.4B) NVIDIA 57% Other nine 43% TRENDFORCE, APRIL 2026. TOP 10 REVENUE UP 44% FROM 2024. MARVELL GIVEN AS MORE THAN $8B; QUALCOMM AND NOVATEK APPROXIMATE.
Top 10 revenue, 2025
$359.4B+
NVIDIA share
57%
Top 10 growth
+44%
2nm design cost
About $725M (IBS)
China design firms
3,901
Hub
Materials

Scale

NVIDIA Earns More Than the Next Nine Fabless Companies Combined

A fabless company designs chips and sells them but owns no wafer fab. It buys wafers from a foundry, packaging and test from an outsourced assembly and test company (OSAT), and rents its design software. The model now holds most of the industry's value. TrendForce counts more than $359.4 billion of 2025 revenue at the top 10 fabless companies, up 44% from 2024, and NVIDIA earned $205.7 billion of it, 57% of the total and more than the other nine combined.

The ranking is a map of the AI build-out. NVIDIA, Broadcom (custom accelerators and networking), AMD and Marvell grew 30% to 65%, while the phone and PC suppliers, Qualcomm, MediaTek, Realtek and Novatek, grew 1% to 16%. The leaders rely on Taiwan: TSMC makes the main products of NVIDIA, Broadcom, Qualcomm, AMD, MediaTek and Marvell, and Realtek and Novatek use TSMC and UMC.

Design to silicon

A Fabless Chip Passes Through Five Other Companies Before It Ships

How a fabless chip reaches silicon. The fabless company writes the design and licenses processor and interface IP. EDA software turns the design into a layout checked against the foundry process design kit. The layout goes to a mask shop, then to the foundry for wafers, then to an OSAT for packaging and test, and the finished chips ship back to the fabless company, which sells them. The fabless company owns no factory at any step. Fabless company ARCHITECTURE, RTL Licensed IP ARM, SYNOPSYS, CADENCE EDA software SYNTHESIS TO SIGN-OFF Foundry PDK RULES AND MODELS GDSLAYOUT Mask shop PHOTOMASKS Foundry WAFERS OSAT PACKAGE AND TEST Chips sold BY THE FABLESS FIRM OWNED BY THE FABLESS COMPANY: DESIGN, IP CHOICES, CUSTOMER. RENTED: EDA LICENSES. BOUGHT AS A SERVICE: MASKS, WAFERS, PACKAGING, TEST. A LEADING-EDGE DESIGN AT 2NM IS ESTIMATED AT ABOUT $725M BEFORE THE FIRST WAFER (IBS, FOR A FIRM WITH NO PRIOR IP).

The design leaves the fabless company as a layout file and comes back as packaged chips. Each handoff in between is a separate market: IP licensing, EDA software, the foundry's process design kit, photomasks, wafers and packaging and test.

Segments

AI Chips Grew Fastest; Phone and PC Chips Grew Least

Fabless segments and their leaders, 2025
SegmentLeadersMain productsMain foundry
AI accelerators and GPUsNVIDIA, AMDData center GPUs, AI accelerators, gaming GPUsTSMC N4 and N3; CoWoS packaging
Custom silicon and networkingBroadcom, Marvell, Alchip, GUCHyperscaler AI chips (Google TPU, Meta MTIA), Ethernet switch chips, optical DSPsTSMC
Phone and PC processorsQualcomm, MediaTek, Apple (designs its own; not counted as fabless)Phone processors, modems, PC chipsTSMC; some Samsung
Connectivity and displayRealtek, Novatek, HimaxWi-Fi and Ethernet chips, display drivers, timing controllersTSMC, UMC
Image sensorsOmniVisionPhone, auto and security camera sensorsTSMC, Huali, others
Power and analogMPS (Monolithic Power Systems)Power modules and regulators for AI servers and carsFoundry partners on its own BCD processes
RISC-V and edgeSiFive, Andes, Tenstorrent, SpacemiTRISC-V cores and processors, AI chipsTSMC, Samsung, SMIC

Design cost

A 2nm Design Costs About $725 Million Before the First Wafer

The cost of a leading-edge design limits who can afford one. IBS, an industry cost analyst, estimated about $725 million to design a chip at 2nm, including about $314 million for software and about $154 million for verification, for a company starting with no reusable IP. A full mask set adds tens of millions of dollars at every tape-out (see Photomasks and Reticles), and a second spin repeats most of it. Those costs keep leading-edge design to firms with tens of billions of dollars in revenue, and they push others onto older nodes or into chiplets that reuse dies already paid for.

China

China Has 3,901 Design Firms, Most of Them Small

China's chip design industry, 2025
MeasureFigureNote
Chip design companies3,901Up from 3,626 in 2024 (ICCAD, via TechNode)
Industry revenueAbout $118BUp 29.8%
Firms earning over RMB 100M8312,061 earn under about $1.4M
Processors as a share of revenueAbout 7.7%Against about 25% worldwide
Leading firmsHiSilicon (Huawei), UNISOC, Will Semi (OmniVision parent), GigaDevice, Cambricon, LoongsonHiSilicon designs Ascend and Kirin chips made at SMIC
Main dependenciesUS EDA software; TSMC and Samsung for advanced designsFirms on the US Entity List are cut off from TSMC advanced nodes

Chokepoints

Five Chokepoints Sit Between a Design and Its Chips

Where the design layer can be cut off
ChokepointWho holds itWhat happens if it is cut
EDA softwareSynopsys, Cadence, Siemens EDANo synthesis, layout or sign-off; a 2025 US license requirement stopped China sales for six weeks
Processor IPArm; RISC-V as the open alternativeNo licensed CPU cores for phones, cars and servers
Leading-edge wafersTSMCNo production path below 5nm outside Taiwan except Samsung and Intel
Advanced packagingTSMC CoWoS, then ASE and AmkorAI accelerators wait for packaging capacity, not wafers
Foundry access rulesUS Commerce DepartmentDesigns at 16/14nm or below need an approved designer or packager path (2025 rule)

Record

Page Record

Covers
Fabless model, 2025 ranking, design-to-silicon handoffs, segments, design cost, China's design industry and chokepoints
Sources
TrendForce top 10 fabless ranking for 2025 (April 2026); IBS design cost estimate via Nikkei Asia (January 2024); ICCAD 2025 figures via TechNode (December 1, 2025); BIS foundry due diligence rule (January 2025); Caixin on the 2025 EDA license requirement
Last verified
October 2026