Back-End Assembly

Assembly flow

Five Steps Turn a Sorted Wafer Into Packaged Parts

Back-end assembly takes the tested wafer from the fab and returns individually packaged, tested chips ready for a circuit board.

A sorted wafer arrives from wafer sort with a map of which dies passed. Traditional assembly takes one to two weeks from that point to a tested part, and it accounts for roughly 10% to 20% of the cost of a finished chip. Unlike the front end, nothing loops: each step runs once per die or once per package.

Wire bond and flip-chip

Wire Bond Ships the Most Units; Flip-Chip Ships the Value

Few parts sit near the line. A $2 MCU in a quad flat no-lead (QFN) package stays on wire bond, and a GPU in a flip-chip ball grid array (FCBGA) stays on flip-chip. Copper pillar bumps, a fine-pitch flip-chip form, have moved some mid-range FPGAs, embedded processors and networking chips across. Copper-to-copper hybrid bonding, used in TSMC SoIC and Intel Foveros Direct, belongs to advanced packaging and is covered on Advanced Die Interconnects.

Package types

Package Choice Follows Pin Count and Power

Cost and wiring density rise together down the table, from a QFN that sells for cents to a CoWoS module that carries an AI accelerator worth tens of thousands of dollars. Leadframe and wire-bond packages still ship the most units; flip-chip and advanced packages carry most of the value.

Equipment

A Few Toolmakers Hold Each Step

Apart from test (Teradyne, Cohu) and Applied Materials' hybrid bonding work with BESI, the back-end tool leaders are based in Japan, the Netherlands, Singapore and Hong Kong. Kulicke & Soffa was founded near Philadelphia and now runs from Singapore.

Who assembles

Taiwan and China Hold Most Outsourced Assembly

Outsourced assembly and test (OSAT) companies serve fabless chip designers and take overflow from integrated device makers. Most IDMs, including Intel, Texas Instruments, Infineon, STMicroelectronics, Samsung, SK hynix and Micron, run their own assembly lines, mostly in Southeast Asia and China. TSMC now assembles its own CoWoS and SoIC modules. The full operator view is on OSAT Landscape, IDM Captive Packaging and Foundry Captive Packaging.

US assembly

US Volume Assembly Starts in 2028, and Only for Advanced Packages

The United States assembles a small share of the world's chips, and almost none of its mainstream packages. DIGITIMES projected in April 2026 that US packaging capacity would reach about 10% of the world's by 2032 as the plants below come online. Amkor's $7 billion Peoria campus, with $407 million in CHIPS Act funding, will be the first US high-volume advanced packaging plant run by an OSAT.

• Made in US
• US planned
• Made abroad

The US plants are all advanced packaging. QFN, SOIC and wire-bond BGA assembly for MCUs, analog and power chips stays in Malaysia, the Philippines, Vietnam, Thailand and China, and no announced US project changes that.

Advanced packaging

Advanced Packaging Adds Steps Between Attach and Mold

Advanced packaging adds steps between die attach and encapsulation: interposer and redistribution-layer builds, chip-on-wafer bonding, through-silicon-via reveal and multi-die stacking. Those steps are run by foundries (TSMC, Intel, Samsung), memory makers (SK hynix, Samsung, Micron for HBM) and the largest OSATs (ASE, Amkor, JCET). TSMC CoWoS capacity is the binding limit on AI accelerator supply. The platforms are covered under Packaging, starting with CoWoS and the packaging matrix.

Related coverage

Related Coverage

• Manufacturing Process Flow
• Wafer Sort Test
• Dicing
• Die Attach
• Wire Bonding
• Flip-Chip Bonding
• OSAT Landscape
• Packaging Overview