Test Equipment Overview

Test equipment is the third major pillar of semiconductor manufacturing equipment, alongside Wafer Fab Equipment (front-end transformation of wafers) and Packaging Equipment (back-end assembly of packaged chips). Every chip in production is tested before it ships — at wafer level (to identify known-good dies), after packaging (to verify the completed package functions), and often at system level (to catch defects that pattern-based tests miss). Test equipment categories serve these test phases with specialty tools: ATE (Automated Test Equipment) systems that apply electrical test patterns and measure device responses; probe cards that form the electrical interface between ATE and devices under test at wafer probe; wafer probers that mechanically position wafers for probe-card contact; handlers that move packaged devices through test; plus specialty categories including burn-in systems, system-level test (SLT) platforms, and failure analysis equipment.

The industry structure is concentrated at each category. Advantest (Japan) and Teradyne (US) together control approximately 80%+ of the global ATE market, making ATE a duopoly with concentration comparable to several of the narrow WFE duopolies. Probe cards are an oligopoly led by FormFactor (US, global leader), Technoprobe (Italy), and Japan Electronic Materials (JEM) plus specialty operators. Wafer probers concentrate at Tokyo Electron (TEL) with the Precio platform dominant globally. Handlers concentrate at Cohu (US). Each category has its own structural concentration pattern, and three categories specifically — HBM test capacity, advanced probe cards for sub-5nm logic and HBM, and system-level test for AI accelerators — have become binding constraints on AI accelerator and advanced memory shipment volumes.

This hub catalogs test equipment through the equipment and vendor lens — who makes the tools, how the categories are organized, and where the strategic concentrations are. A parallel set of pages covers test through the process discipline lens at Final Test and Advanced Packaging Test. Facility-level coverage for dedicated test operators is at Standalone Test Houses.

The Test Equipment Categories

Test equipment decomposes into seven primary categories. The categories are sequential in the test flow — a wafer passes through wafer probe (prober + probe card + ATE), then packaging, then final package test (handler + ATE), then optionally SLT and burn-in. The table below maps each category to its test role and leading vendors.

The categories are not independent. A complete test line requires ATE + probe card + prober for wafer probe, plus ATE + handler for final test, plus potentially SLT and burn-in. The bottleneck category at any given test line depends on the specific products being tested — HBM-heavy operations have HBM-ATE as the binding resource, AI-accelerator-heavy operations have SLT as binding, high-volume commodity memory has handler throughput as binding.

The Advantest-Teradyne ATE Duopoly

The ATE market has been a two-operator duopoly between Advantest and Teradyne for most of the past two decades. Combined market share is approximately 80%+ of global ATE revenue, with smaller specialty vendors serving specific segments. The duopoly has distinct product specializations reflecting different historical strengths.

Advantest (Tokyo, Japan) operates the V93000 as its flagship ATE platform — a single-platform architecture that scales across logic and memory testing applications. V93000 is the industry reference for memory test, and Advantest has leveraged its memory test strength into dominant HBM testing position. The Advantest relationship with SK hynix and Samsung Memory on HBM test is structurally important — HBM capacity at the memory IDMs scales with Advantest HBM test capacity at the downstream test flow. Advantest has also expanded into SLT and is positioning for AI accelerator test growth.

Teradyne (North Reading, MA) operates a portfolio of test platforms: FLEX and UltraFlex for advanced SoC test, Eagle Test Systems for specialty, and J750 for high-volume microcontroller and commodity test. Teradyne has historical strength in SoC test — mobile processors, automotive SoCs, networking chips — and has grown SLT and AI accelerator test capabilities. Teradyne's acquisition history includes Eagle Test Systems, Nextest, and specialty operations that expanded its product breadth.

The competitive dynamic between Advantest and Teradyne has been relatively stable. Advantest dominates memory test and HBM test where the V93000 platform has particular advantages. Teradyne dominates high-volume commodity test (J750 platform) and has historically been stronger in SoC applications. Both operators have expanded into SLT and are positioning for AI accelerator test growth. Customer loyalty is substantial — test engineering organizations develop deep expertise on specific ATE platforms, and switching platforms requires substantial retraining and re-tooling of test program development.

The Probe Card Oligopoly — An Underappreciated Specialty Supply Chain

Probe cards are the specialized interface between ATE and the wafer during wafer-level probe test. A probe card for a modern advanced-node SoC contains thousands of micro-contacts (cantilever beams, vertical springs, or specialty MEMS-style probe tips) that must make electrical contact with device pads at specific positions with controlled force and electrical characteristics. Each probe card is designed for a specific product — there is no generic probe card. A new product or new process node typically requires a new probe card design and qualification.

Probe cards are consumables. The probe tips wear through the tens of thousands of touchdowns they perform during test, and require replacement after predictable wear lifetimes. High-volume test operations consume thousands of probe cards per year, making probe card supply a volume commodity consumable rather than a one-time capital purchase. But probe card design is specialty engineering — new advanced-node probe cards for leading-edge logic and HBM testing are among the most demanding engineering challenges in the test industry.

The probe card supplier base is oligopolistic. FormFactor (Livermore CA) is the global leader with broad product portfolio across logic, memory, and specialty probe cards; the 2016 acquisition of Cascade Microtech expanded FormFactor's position into specialty applications. Technoprobe (Italy) has grown to significant global position particularly in high-performance logic probe cards. Japan Electronic Materials (JEM) has specialty strength at Japanese customers and in specific probe card categories. Micronics Japan, MPI (Taiwan), and specialty operators serve specific segments.

Advanced-node probe cards for sub-5nm logic and HBM testing represent a specific strategic concentration. The engineering requirements — tight pitch (sub-50µm), precise contact force, controlled impedance across thousands of channels, thermal stability — are met by a small number of suppliers globally. FormFactor and Technoprobe have been competing intensively for advanced-node probe card design wins at TSMC, Samsung, and Intel leading-edge customers. HBM-specific probe cards for stacked memory test represent another specialty category where capability concentrates at a small number of suppliers. Probe card capacity is a less-discussed but structurally significant constraint on advanced-node test throughput.

HBM Test as the Structural Growth Category

HBM (High-Bandwidth Memory) testing has emerged as the highest-value-growth test equipment category over the past three years, driven by the explosive growth in AI accelerator production and the associated HBM stack demand. HBM testing is fundamentally different from commodity DRAM testing in several dimensions. Test times are substantially longer — full functional + protocol + DRAM cell + thermal testing per HBM stack runs to hours, compared to minutes per commodity DRAM. Test equipment requirements are specific — high-pin-count ATE, specialty stacked-memory test sockets, thermal heads for controlled-temperature testing. Test volumes are scaling with AI accelerator demand — HBM production is doubling annually, and HBM test capacity must scale in parallel.

The Advantest V93000 platform is the industry reference for HBM test at the memory IDMs (SK hynix, Samsung Memory, Micron). Advantest's relationships with the memory IDMs and with NVIDIA on HBM test architecture have established Advantest as the dominant HBM test ATE supplier. Teradyne has HBM test capability but the market position has been weaker than in SoC test. Specialty HBM test operations at KYEC (King Yuan Electronics) and other standalone test houses (see Standalone Test Houses) increasingly serve external HBM test demand beyond captive memory IDM capacity.

The HBM test capacity story parallels the HBM packaging capacity story — both are binding constraints on AI accelerator shipment volume. An HBM stack that passes hybrid bonding assembly must then pass KGS (known-good-stack) testing before it can be integrated into a CoWoS module. The full chain of capacity constraints (HBM wafer production at the memory IDMs + hybrid bonding at memory IDM captive packaging + HBM test at Advantest ATE + CoWoS integration at TSMC + final AI accelerator test) must all scale together for AI accelerator shipment to scale. Advantest HBM test capacity is one of the less-discussed links in this chain but structurally significant.

System-Level Test (SLT) — The AI Accelerator Test Growth Category

System-Level Test (SLT) runs actual application workloads on devices under test rather than pattern-based ATE tests. The distinction matters because pattern-based ATE tests can miss certain defect mechanisms that only manifest under real-workload conditions — race conditions, cache coherency issues, specific memory access patterns, and power transient behaviors that are difficult to stimulate with synthetic test vectors. SLT catches these defects by operating the device as a system component rather than as a pattern-stimulated DUT.

SLT is capital intensive. Each SLT slot is essentially a miniature system — motherboard or carrier board with peripheral components, power delivery, thermal management, interfaces to test controllers. A single SLT system can test only one device at a time per slot, and the slot cost is substantial ($20K–$200K+ per slot depending on complexity). High-volume SLT operations run thousands of slots in parallel, producing capital costs comparable to complete ATE floors.

SLT has become particularly important for AI accelerators, flagship SoCs, and high-reliability products where pattern-based ATE coverage is insufficient. Every NVIDIA H-series and B-series GPU passes through SLT; AMD MI-series accelerators use SLT; Google TPU and hyperscaler custom AI silicon use SLT extensively. The growth of SLT at AI accelerator operators has driven capital investment in SLT infrastructure at both captive test operations (TSMC, Samsung advanced packaging facilities) and merchant test operators (KYEC and standalone test houses). Cohu and Advantest are the primary SLT platform vendors.

Test Equipment Cost Structure

Test equipment tool costs scale dramatically across the commodity-to-advanced spectrum, similarly to packaging equipment but with different specific cost drivers.

The probe card cost — consumable at $500K–$2M per card for advanced-node applications — illustrates a distinctive test equipment economics dimension. Unlike ATE which is a one-time capital purchase amortized over years, probe cards are recurring consumables. A high-volume HBM test operation might consume probe cards at $10M+ annually just in probe card replacement. This consumable cost structure makes probe card supply chain stability as important as ATE supply — and given the oligopolistic probe card supplier base, probe card supply disruption can affect test throughput quickly.

Vendor Structure

Test equipment vendors fall into several categories reflecting their product breadth and strategic positioning.

ATE primary vendors. Advantest and Teradyne together dominate ATE globally. Both operate broad platform portfolios and have expanded into adjacent categories (SLT, specialty test). Advantest has stronger memory and HBM test position; Teradyne has stronger SoC and commodity microcontroller test position.

Specialty test category leaders. FormFactor leads probe cards globally. Cohu leads handlers and SLT. Tokyo Electron (TEL) leads wafer probers (extending TEL's WFE presence into test equipment). Hitachi High-Tech leads specialty failure analysis electron-beam systems. Each of these operators has deep category-specific expertise.

Specialty probe card suppliers. Technoprobe (Italy) has grown to significant global probe card position competing with FormFactor in advanced applications. Japan Electronic Materials (JEM), Micronics Japan, and MPI (Taiwan) serve specific segments. The probe card vendor structure is more fragmented than ATE but still oligopolistic at the advanced-node level.

Cross-WFE test equipment. Tokyo Electron (TEL) operates in both WFE and test (wafer probers). KLA operates in both WFE (inspection and metrology) and test (specialty FA). The boundary between advanced inspection and test is increasingly blurry at advanced nodes where device characterization, defect analysis, and functional test interact more tightly.

Cross-Coverage — Test Equipment in Context

Test equipment interacts with multiple other pillars of the SiliconPlans network:

Process-activity lens pages cover what happens physically during test steps: Final Test covers the post-packaging test flow; specialty wafer test coverage is in the back-end assembly tree.

Test discipline coverage at Advanced Packaging Test covers the specific disciplines — KGS (known-good-stack), SLT (system-level test), HBM test framework — that advanced test equipment enables.

Facility-level test coverage at Standalone Test Houses covers the merchant test operators (KYEC, ISE Labs, Ardentec, Sigurd, specialty DMEA-accredited test) that operate test equipment as their primary business.

Cross-pillar test customers include all the operators and facilities that use test equipment in production: Wafer Fabs for wafer probe, Packaging & Test Facilities for final test, IDM Captive Packaging for memory and specialty test, Foundry Captive Packaging for advanced packaging test.

Export Controls and Strategic Positioning

Test equipment has been less prominent than WFE in US and allied export control regimes, but specific advanced test categories are increasingly covered. Advanced HBM test equipment and specialty advanced-node test systems face restrictions on export to Chinese advanced memory and logic operators. Traditional test equipment (commodity ATE, standard handlers, mature probe cards) remains largely unrestricted.

Chinese domestic test equipment capability is scaling. ChipWare, specialty Chinese ATE operators, and domestic probe card suppliers serve mature-node Chinese test with capability gaps at advanced test categories. The Chinese test equipment advancement trajectory parallels the Chinese domestic WFE and packaging equipment stories — mature-node self-sufficiency is broadly achievable, but advanced test equipment capability requires closing IP and engineering gaps against Advantest, Teradyne, and specialty vendors. HBM test specifically is the most acute Chinese capability gap.

Related Coverage

Parent: Fab & Assembly

Peer equipment hubs: Wafer Fab Equipment · Packaging Equipment

Process-activity lens: Final Test

Test discipline coverage: Advanced Packaging Test (KGS, SLT, HBM test framework)

Facility-level coverage: Standalone Test Houses · Packaging & Test Facilities

Vendor profiles (planned): Advantest · Teradyne · FormFactor · Cohu · Tokyo Electron · Technoprobe

Cross-pillar dependencies: HBM (HBM test capacity as binding constraint) · AI Accelerators (SLT growth driver) · Automotive MCUs (reliability test / burn-in)