Final Test

Final test, burn-in and system-level test · Advantest, Teradyne, Cohu, KYEC

Final test checks every packaged chip before it ships and sets its product grade. An AI accelerator spends well over 20 minutes on the tester, against under a minute for a phone processor, and NVIDIA expects to double its test capacity from 2026 to 2027, including new KYEC test sites in the United States.

Time on the tester per chip: about 30 to 60 seconds for a 5nm-class phone processor, and well over 20 minutes for a Blackwell-class AI accelerator. Test cost has risen from under 2% of chip price toward 5 to 7% on complex AI packages. NVIDIA expects its test capacity to double from 2026 to 2027, and is advancing 1.1 billion dollars to KYEC for new US test sites. MINUTES ON THE TESTER PER CHIP Phone processor, 5nm 30 TO 60 SECONDS AI accelerator WELL OVER 20 MINUTES AI DIES NEED TWO TO THREE TIMES THE TEST PATTERNS OF A 7NM-ERA PHONE CHIP. TEST COST AS A SHARE OF CHIP PRICE Before Under 2% Complex AI packages 5 to 7% NVIDIA TEST CAPACITY 2x From 2026 to 2027, in the US, Taiwan and Singapore; a $1.1B advance funds new KYEC test sites in the US TEST TIME AND COST: WING VC, MAY 2026. CAPACITY: NVIDIA, OCTOBER 21, 2026.
Phone SoC test time
30 to 60 s
AI accelerator
20+ min
Test cost, AI
5 to 7% of price
NVIDIA capacity
2x, 2026 to 2027
US test sites
KYEC, from 2027
Hub
Process

Role

Final Test Is the Last Check Before a Chip Ships

Final test is the last check before a packaged chip ships. Wafer sort, covered on Wafer Sort Test, keeps bad dies out of packages. Final test catches what assembly breaks, such as cracked bumps, broken wire bonds and mold stress, and confirms full performance at the package's operating temperature. It also sets the product grade: which speed, power or core count each chip is sold as.

For a phone processor final test takes under a minute. For an AI accelerator it takes over 20 minutes on the tester, and is followed by burn-in and system-level test. That gap is why test has become a capacity constraint for AI chips.

Test insertions

AI Chips Add Burn-In and System-Level Test

Test insertions for two kinds of chip. A phone processor goes from wafer sort to assembly to final test and ships. An AI accelerator goes from wafer sort, often with extra known-good-die coverage, to assembly, final test with active thermal control, burn-in, and system-level test on a board running real software before it ships. Phone processor Wafer sort Assembly Final test Ship AI accelerator Sort and KGD Assembly Final test Burn-in System test Ship TEST STEPS IN GRAY, ASSEMBLY IN GREEN. EACH ADDED INSERTION MEANS MORE TESTERS, HANDLERS AND SOCKETS PER CHIP.

System-level test (SLT) runs the packaged chip on a board that looks like the real product, booting software and running workloads, to catch faults that structural test patterns miss. It began with phone and PC processors and now covers AI accelerators and the chips around them. Burn-in stresses parts at high temperature and voltage for hours to bring out early-life failures, and is standard for automotive, medical and defense parts. Some burn-in has moved to wafer level for AI processors: Aehr Test Systems reported a $22 million follow-on order for AI processor wafer-level burn-in systems in August 2026.

Test cell

A Handler and a Tester Work Each Part

Final test cell steps
StepWhat happensWhat goes wrong
PickHandler takes a packaged part from a tray, tube or reelPackage damage, bent leads
InsertPart is pressed into a socket whose contacts touch every ball or leadWorn or dirty contacts, false failures
SoakThermal head or chamber brings the part to test temperatureSelf-heating: an AI chip under test can draw hundreds of watts
TestTester runs the program: DC, functional, scan, speedEscapes that pass bad parts; over-testing that fails good ones
Bin and packHandler sorts each part by result into trays or tape and reelMis-binning, wrong orientation

High-volume cells test four, eight, 16 or more parts at once to spread the tester's cost. High-power AI parts need active thermal control: heads that pump liquid to heat or cool the chip while it runs, from Advantest, Cohu and a few specialists.

Test types

A Test Program Runs Several Kinds of Test

Final test types
TypeWhat it checksUsed on
Parametric (DC)Leakage, supply current, threshold and input and output levelsEvery part
FunctionalLogic, memory and analog paths at operating conditionsLogic, memory, SoCs, mixed-signal
Scan and structuralPatterns through internal scan chains reach every flip-flopComplex logic
Speed binningTop clock, power and working cores, for product gradesCPUs, GPUs, AI accelerators
Burn-inEarly-life failure under heat and voltage for hoursAutomotive (AEC-Q100), medical, defense, AI
System-level testReal software on an application-like boardPhone, PC and AI processors

Equipment

Testers, Handlers and Sockets Come From Specialists

Final test equipment
EquipmentMain suppliersNotes
Testers (ATE)Advantest, Teradyne; Changchuan Technology and Huafeng in ChinaSame platforms as wafer sort; Advantest held about 65% of the 2025 market
HandlersCohu, Advantest, Chroma ATE, Hon PrecisionPick-and-place, turret and gravity handlers; thermal control
Test socketsLeeno Industrial, ISC, Yamaichi, Smiths Interconnect, CohuConsumables replaced after a set number of insertions
System-level testAdvantest, Teradyne, Cohu, ChromaRacks of application boards; a multi-billion dollar add-on to ATE
Burn-inAehr Test Systems (wafer level), KES Systems, Micro Control, ChromaOvens and boards; wafer-level systems for SiC and AI processors

Sites

NVIDIA Is Paying to Double Its Test Capacity

Most final test for leading-edge chips happens in Taiwan, at KYEC, ASE and SPIL, and at OSAT sites in Southeast Asia and China. On October 21, 2026 NVIDIA said it expects its total test capacity to double from 2026 to 2027 across the United States, Taiwan and Singapore, and that it is advancing $1.1 billion to KYEC for new US test facilities and equipment.

  • Made in US
  • US planned
  • Made abroad
Final test sites for AI accelerators
SiteLocationMakesStatusUS status
KYEC TaiwanHsinchu and Miaoli, TaiwanWafer sort, final test and SLT for AI acceleratorsOperatingMade abroad
KYEC US test sitesUnited States, sites not namedNew test capacity funded by a $1.1B NVIDIA advanceHigh-volume production targeted for April 2027US planned
Expanded NVIDIA test operationsSingaporeTest capacity for NVIDIAHigh-volume production targeted for February 2027Made abroad
ASE and SPILKaohsiung and Taichung, TaiwanFinal test bundled with assemblyOperatingMade abroad
Amkor ArizonaPeoria, AZAdvanced packaging and test for TSMC Arizona wafersProduction from early 2028US planned
Placeholder: remaining test sites from the fab dataset

Test houses and OSATs are profiled on Test Houses and OSAT Landscape.

Record

Page Record

Covers
Final test role, test insertions, test cell, test types, equipment and sites
Sources
Wing VC, The Chip Testing Bottleneck (test time, test cost share, May 2026); NVIDIA release (test capacity and KYEC advance, October 21, 2026); Aehr Test Systems release (August 2026); Advantest market figures via Wing VC
Last verified
October 2026