Adv Packaging
EMIB
EMIB (Embedded Multi-Die Interconnect Bridge) is Intel’s 2.5D packaging technology that uses a small embedded silicon bridge within a package substrate to connect multiple dies. Unlike large silicon interposers used in CoWoS, EMIB places only the necessary interconnects under adjacent dies, reducing cost and improving scalability. EMIB is a cornerstone of Intel’s advanced packaging portfolio and is often combined with Foveros for hybrid 2.5D + 3D integration.
Process Overview
- Step 1: A small silicon bridge with high-density wiring is embedded into the organic substrate.
- Step 2: Adjacent dies (logic, memory, accelerators) are flip-chip bonded onto the bridge area.
- Step 3: Fine-pitch interconnects across the bridge provide die-to-die communication.
- Step 4: The package is completed with underfill, encapsulation, lid attach, and system-level test.
Key Features
- Localized Interconnect: Bridges only where needed, reducing silicon area vs full interposers.
- High Bandwidth: Supports fine-pitch, high-density I/O for multi-die integration.
- Cost-Effective: Avoids expensive large silicon interposers while enabling 2.5D performance.
- Scalability: Supports multiple bridges in a single package, enabling complex multi-die topologies.
Applications
- FPGAs: Intel Stratix 10 and Agilex devices use EMIB for logic + transceiver integration.
- CPUs + Accelerators: Used in Intel Xeon processors paired with discrete GPUs/accelerators.
- GPUs/AI: Ponte Vecchio GPU combines EMIB and Foveros for extreme compute density.
Representative Products
| Product | Type | EMIB Role |
|---|---|---|
| Intel Stratix 10 | FPGA | EMIB connects FPGA core to transceivers and HBM |
| Intel Agilex | FPGA | Uses EMIB for heterogeneous integration of logic and analog dies |
| Intel Ponte Vecchio | AI/HPC GPU | Combines EMIB and Foveros to integrate >40 chiplets |
Advantages & Constraints
- Advantages: Lower cost vs interposers; localized silicon bridges reduce warpage; highly flexible for multi-die layouts; can be combined with Foveros.
- Constraints: Interconnect density lower than full interposers; alignment precision critical; requires new design methodologies and EDA support.
Cleanroom & Environment
- Assembly typically performed in Class 1000–10,000 packaging areas.
- Die attach and bridge placement require micron-level alignment tolerances.
- Thermal and stress management still critical, especially in high-power FPGA and GPU modules.
Market Outlook
EMIB is one of Intel’s competitive differentiators in advanced packaging, enabling cost-effective 2.5D integration. Its modular approach complements Foveros for hybrid architectures. As chiplet adoption grows across CPUs, GPUs, and FPGAs, EMIB is expected to expand in HPC and datacenter applications. Competing approaches (CoWoS, I-Cube) provide alternatives, but Intel’s EMIB + Foveros integration strategy is unique in the industry.