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Semiconductor Wafer Polishing & Surface Prep



After slicing, a silicon wafer is mechanically damaged, bowed, and rough -- entirely unsuitable for lithography. The polishing sequence removes saw damage, achieves micron-level flatness, and ultimately delivers a sub-nanometer mirror surface. This is a multi-step process: mechanical lapping removes bulk damage and controls thickness; chemical etching removes residual stress; double-side polishing achieves global flatness; and single-side CMP delivers the final mirror finish required by advanced lithography tools. Each step sets the input quality for the next, and a failure to remove damage at an early stage propagates into subsequent steps at increasing cost.

Polishing Process Sequence

Step Process Material Removed Flatness Achieved Key Consumables
1. Edge Grinding & Profiling Diamond grinding wheel rounds and profiles the wafer edge to a defined radius; removes sharp edges that cause chipping and particle generation in fab handling ~100-200µm from edge region N/A -- edge geometry specification Diamond grinding wheels; Accretech/Tokyo Seimitsu edge grinder
2. Lapping Mechanical grinding of both wafer surfaces between rotating cast-iron lapping plates using alumina or SiC abrasive slurry; removes saw damage and controls thickness and flatness ~20-40µm per side TTV <2µm; bow <30µm Alumina lapping slurry; cast-iron lapping plates
3. Chemical Etching Immersion in acid (HF/HNO3/acetic acid -- HNA etch) or alkaline (KOH or NaOH) etchant removes residual mechanical damage and surface stress from lapping; isotropic acid etch or anisotropic alkaline etch ~10-20µm per side Removes subsurface damage; slight roughening of surface (Ra ~0.3-1µm) HF, HNO3, acetic acid (acid etch) or KOH (alkaline etch); ultrapure DI water rinse
4. Double-Side Polishing (DSP) Both wafer surfaces polished simultaneously on carrier between upper and lower polishing plates using colloidal silica slurry; achieves global flatness without introducing new bow ~5-10µm per side GBIR <1µm; TTV <0.5µm; Ra ~0.5nm Colloidal silica slurry (Fujimi GLANZOX series); polyurethane polishing pads; carrier wafers
5. Single-Side CMP (Final Polish) Chemical-mechanical polishing of front surface only; removes DSP-induced surface micro-roughness; final mirror finish achieved through combination of colloidal silica chemistry and pad pressure <1µm Ra <0.1nm RMS; SFQR <100nm (site flatness); LPD <30 at 90nm threshold for 300mm prime Alkaline colloidal silica slurry (Fujimi GLANZOX, Entegris/CMC SiLECT); soft polishing pads
6. Final Cleaning SC-1 (NH4OH/H2O2/DI) and SC-2 (HCl/H2O2/DI) RCA clean sequence; HF dip for native oxide removal; Marangoni drying with IPA vapor to achieve particle-free surface Particles, organic contamination, metallic ions, native oxide Contamination control: metal impurities <10^10 atoms/cm²; particles <20 at 65nm threshold NH4OH, H2O2, HCl, HF, IPA (all UHP grade); ultrapure DI water (>18 MΩ·cm)

Prime Wafer Surface Specifications (300mm)

Specification Metric Typical Limit Significance
Global flatness (GBIR) Global Back-side Ideal Range <2µm Overall wafer bow; affects chuck contact uniformity across full wafer during exposure
Site flatness (SFQR) Site Front-side least sQuares Range <130nm (ArF immersion); tighter for EUV Local flatness within each exposure field (26×33mm); drives lithography focus margin at advanced nodes
Surface roughness (Ra) Arithmetic mean roughness <0.1nm RMS Sub-angstrom surface finish required for gate oxide integrity and resist adhesion
Light point defects (LPD) Particle count at specified detection threshold <20 particles at 65nm threshold Particles on the wafer surface become lithography defects; specification tightens with each node
Crystal-originated pits (COP) Vacancy cluster density from CZ oxygen Near-zero for advanced gate oxide application COPs degrade gate oxide integrity; managed through CZ process control and hydrogen anneal
Metal contamination Surface metal atoms/cm² <10^10 atoms/cm² for critical metals (Fe, Cu, Ni) Metallic impurities degrade minority carrier lifetime and gate oxide; sourced from process chemicals, equipment, and handling

Additional Steps for Epi and SOI Wafers

Polished prime wafers can be delivered as-is for fabs that perform their own epitaxy. Epi wafers require an additional CVD epitaxy step (typically 1,100-1,200°C in an epitaxial reactor using trichlorosilane or silane precursor) after the prime polish, growing a lightly doped silicon layer of specified thickness on the polished surface. The epi surface must then meet the same or tighter flatness and roughness specifications as a prime wafer, requiring a final light CMP pass in some cases.

SOI wafers (produced primarily by Soitec using Smart Cut technology) bond a thin silicon device layer to an oxidized handle wafer, then cleave the donor wafer at the ion-implanted hydrogen plane, leaving a thin silicon film on the BOX layer. The transferred silicon surface requires CMP to smooth the implant-damaged cleavage surface to device-quality roughness. The BOX thickness and silicon device layer thickness uniformity are the critical SOI-specific specifications, measured by ellipsometry across the wafer. Typical FD-SOI device layer thickness uniformity is ±0.5nm across a 300mm wafer -- a specification that requires extraordinary process control at the cleave and CMP steps.

Supply Chain Outlook

Wafer polishing is a mature process, but specifications continue tightening with each node. The SFQR requirement for EUV lithography is stricter than for ArF immersion, and High-NA EUV will tighten it further -- pushing wafer suppliers to invest in more precise DSP and CMP equipment and tighter process control. COP-free wafers (achievable through hydrogen anneal or epi overlay) are increasingly specified for gate-all-around and 2nm-class devices where oxide quality is paramount. The SOI device layer thickness uniformity spec for advanced FD-SOI is already at the ±0.5nm level, and any further FD-SOI node scaling would require tighter specs that push both Smart Cut and post-cleave CMP to their limits.

Related Coverage

Silicon Wafer Production Overview | Materials & IP Hub | Wafer Slicing | Silicon Ingots | Epitaxy & SOI Wafers | Wafer Deliverables | CMP Slurries | Critical Chemicals | Bottleneck Atlas