Wafer Planarization (CMP)

Chemical mechanical planarization (CMP) flattens the wafer surface after every deposition step that leaves topography behind. A wafer that has just been filled with copper sits with metal bulging out of the etched trenches and above the dielectric surface. Without CMP, the next lithography layer cannot be imaged — the scanner's optics require a wafer surface held to sub-nanometer flatness across each exposure field, and stepper depth of focus at advanced nodes is effectively zero tolerance for topography. CMP removes the excess metal, stops precisely at the dielectric surface, and leaves behind a flat, polished wafer ready for the next layer.

CMP is one of the most frequently repeated operations in front-end fabrication. Every metallization pass requires CMP to clear the metal overburden and expose the dielectric. Every inter-metal dielectric deposition requires CMP if the dielectric must be flattened before the next patterning step. Shallow trench isolation formation requires CMP to remove the STI fill overburden. A leading-edge logic chip with 15 or more metal layers plus dielectric and STI steps passes through CMP tools roughly 20 to 30 times over its fab cycle. Equipment concentration is a duopoly: Applied Materials and EBARA together hold the substantial majority of the global CMP tool market. Consumables — slurry and polishing pad — have their own tight supplier base covered under Process Consumables.

How CMP Works

CMP combines chemistry and mechanical abrasion. The wafer is held face-down on a rotating carrier and pressed against a rotating polishing pad soaked in a chemically active slurry. The slurry contains abrasive particles (silica, ceria, or alumina) suspended in a reactive liquid that chemically modifies the surface being polished. The combined effect — chemical softening of the top layer plus mechanical removal by the abrasive — planarizes the wafer at a controlled rate. Crucially, the chemistry and abrasive are tuned so that the target material polishes much faster than the surrounding material, producing a self-stopping process that levels at the dielectric surface when the metal overburden has been cleared.

The process parameters — down force, rotation speeds, slurry flow rate, pad condition, endpoint detection — all affect planarization uniformity. Endpoint detection is critical because stopping too early leaves metal residue that shorts adjacent lines, and stopping too late dishes the metal below the dielectric surface and increases line resistance. Modern CMP tools use optical or motor-current endpoint detection to determine in real time when the polish has cleared. Post-CMP cleaning — covered under Wafer Cleaning — is mandatory to remove slurry residue and any metal contamination before the wafer moves to the next step.

Where CMP Runs in the Flow

CMP is invoked at multiple distinct points. Each application has its own slurry chemistry, pad selection, and process recipe.

Slurry & Pad Consumables

Every CMP pass consumes two primary consumables. Slurry is a liquid suspension of abrasive particles — typically silica (for oxide polish), ceria (for STI and oxide with higher selectivity), or alumina (for tungsten and specialty applications) — combined with chemistry tuned to the target material. The polishing pad is a porous polyurethane disc that holds the slurry and provides the mechanical surface that abrades the wafer. Both are consumed during operation: slurry is delivered continuously and flushed away, and the pad wears down over time and is replaced on a regular schedule.

Slurry chemistry is formulated per polish. A copper slurry contains hydrogen peroxide or another oxidizer to chemically soften the copper surface, a corrosion inhibitor (benzotriazole or similar) to protect the dielectric, plus the silica or alumina abrasive. A tungsten slurry uses different chemistry because tungsten oxidation behaves differently. An STI slurry uses cerium oxide because ceria provides high oxide-to-nitride selectivity, which is essential for the self-stopping behavior at the STI interface. Each foundry maintains multiple qualified slurry formulations per polish application, and changing slurry suppliers requires a full process re-qualification.

The CMP consumables market is growing faster than overall WFE on a per-wafer basis because the number of CMP passes grows with node advancement and with 3D NAND layer count. The supply chain is concentrated but multi-sourced — dual-qualification of slurry and pads is standard at leading foundries precisely because consumable supply security is operationally critical.

CMP Equipment Vendors

CMP tool supply is effectively an Applied Materials–EBARA duopoly, with specialty tools from a small number of additional vendors. Applied Materials leads globally through its Reflexion and Mirra platforms. EBARA is the primary alternative, with particular strength at Japanese and Korean memory fabs. The tool architectures from both vendors have converged on multi-head planetary designs that polish multiple wafers in parallel to maximize throughput.

Why CMP Complexity Grows with Scaling

CMP has become progressively more demanding as nodes have advanced, along three independent axes. First, the number of CMP passes per wafer grows directly with metal layer count — a 15-layer BEOL stack runs more copper CMP than a 10-layer stack. Second, the materials being polished have diversified: mature nodes polished copper, tungsten, and oxide; advanced nodes add cobalt, ruthenium, low-k dielectrics, and specialty stop layers, each requiring its own slurry chemistry and pad selection. Third, planarity tolerances have tightened as lithography depth of focus has shrunk with EUV — advanced CMP must deliver sub-nanometer within-die uniformity across the exposure field to support EUV patterning.

The consequence is that CMP's share of wafer fab equipment capex has grown, and the CMP consumables market has grown faster still. Each advanced node introduces new slurry qualifications, new pad formulations, and new endpoint detection challenges. 3D NAND scaling from 64 layers to 232+ layers adds proportionally more CMP passes per wafer. Advanced packaging — particularly hybrid bonding for 3D IC and HBM stacking — imposes planarity requirements on wafer surfaces that previous CMP generations could not achieve. CMP is no longer a mature, commoditized step; it is an active area of process innovation that pace-setting foundries treat as a strategic capability.

Related Coverage

Parent: Front-End Fabrication

Peers in front-end: Wafer Cleaning · Oxidation · Deposition · Photolithography · Etching · Doping · Metallization · Metrology

Equipment & consumables: WFE Hub · Process Consumables

Related: Wafer Production Polishing (the pre-fab mirror polish applied to incoming silicon wafers is a distinct activity — supplier-side, not in-fab)

Cross-pillar dependencies: Process Nodes & Lines · Bottleneck Atlas