SMIC SN1/SN2 (N+2/N+3)

SMIC - Shanghai, China - N+2 (7nm-class), N+3 (5nm-class) - Operational

DUV multi-patterning, no EUV; Kirin 9030 on N+3 (TechInsights, Dec 2025); fab attribution per press

Capacity of SMIC SN1/SN2 (N+2/N+3) against the largest leading-edge logic fabs in the SemiconductorX dataset, in thousand wafer starts a month LEADING-EDGE LOGIC FABS, THOUSAND WAFERS A MONTH Intel Ohio New Albany 100 TSMC Fab 18 100 Samsung Pyeongtaek P3 80 Intel Fab 34 60 Samsung Hwaseong S3 60 TSMC Fab 20 50 Intel Fab 52 40 TSMC Fab 21 phase 1 35 Rapidus IIM-1 25 Samsung Taylor Texas 25 TSMC Fab 21 phase 2 20 INDIGO: US FABS. CAPACITY IS THE DATASET ESTIMATE; MOST OPERATORS DO NOT DISCLOSE IT.
Operator
SMIC
Node
N+2 (7nm-class), N+3 (5nm-class)
Wafer
300mm
Capacity
Not disclosed
Opened
Not disclosed
US status
Made abroad

Fab record

Fab Record

Every field of the FAB113 row in the SemiconductorX fab dataset.

Fab record FAB113
GroupFieldValue
IdentityFab IDFAB113
NameSMIC SN1/SN2 (N+2/N+3)
OperatorSMIC
Parent companySMIC
LocationCityShanghai
State or regionShanghai
CountryChina
Region groupChina State
Supply-chain riskHigh
ProcessFab typeLogic
CategoryLeading Edge
Process nodeN+2 (7nm-class), N+3 (5nm-class)
Wafer size300mm
ProductsHuawei Kirin and Ascend
Customers
StatusStatusOperational
Year opened or due
CapacityNot disclosed
US statusMade abroad
SourcesSource
Source linkLink
AustinIO pageNone
Last verified2026-10

Same operator

Other SMIC Fabs

Same type, in the US

Other US Leading-Edge Logic Fabs

Record

Dataset Record

Dataset
SemiconductorX fab dataset (fabs2026), row FAB113
Sources
See the source link in the record
Last verified
2026-10