Incoming Wafer Specifications

Fabs receive wafers against a purchase order that fully defines the substrate -- diameter, material, crystal orientation, conductivity type, resistivity, surface finish, epitaxial configuration, edge geometry, identification marking, and container type. A wafer that fails any incoming specification is rejected before stock-in; it never reaches a process tool. This page covers wafer specifications from the fab's receiving standpoint: what options exist for each attribute, what the specs mean for downstream processing, and what incoming QC verifies before a lot enters the fab.

Standard Diameters & Typical Thickness

Diameter	Common Name	Typical Thickness	Primary Uses	Status
100mm	4-inch	0.5-0.7mm	R&D, MEMS, legacy analog/RF, compound semiconductor devices	Declining; still active in specialty and research fabs
150mm	6-inch	0.6-0.8mm	SiC power devices (dominant), RF GaAs, GaN, MEMS, analog power	Mainstream for SiC; stable for analog/power silicon; no new 150mm silicon capacity being added
200mm	8-inch	0.7-0.9mm	Mixed-signal, analog, image sensors (CIS), SiC power (transitioning), mature node MCUs, automotive	Fully utilized; constrained capacity; IoT/automotive demand outpacing supply
300mm	12-inch	0.75-1.0mm	Leading-edge logic, DRAM, NAND flash, CMOS image sensors (advanced)	Industry standard for advanced nodes; ~75% of silicon wafer market value
450mm	18-inch	~1.0mm	No current production use	Indefinitely deferred; R&D only

Silicon Wafer Attribute Specifications

Attribute	Options / Range	Notes
Crystal Orientation	{100}, {111}, {110}	{100} is the mainstream CMOS orientation; {111} used for MEMS (favorable etch anisotropy with KOH) and some power devices; {110} for specialty high-mobility applications
Conductivity Type	P-type (boron); N-type (phosphorus, antimony, arsenic)	Most CMOS starts on p-type substrate; n-type used for power devices and some sensors; antimony and arsenic dopants used for very low resistivity (heavily doped n+) substrates
Resistivity	~0.001 to >10,000 Ω·cm	Low resistivity (<0.01 Ω·cm) for heavily doped p+ or n+ substrates used in power epi wafers; high resistivity (>1,000 Ω·cm) for RF substrates and image sensors; FZ silicon required above ~5,000 Ω·cm
Surface Finish	Single-side polished (SSP); Double-side polished (DSP)	DSP is standard for 200mm and 300mm FEOL -- backside polish improves chuck contact uniformity in lithography; SSP used for some power and MEMS applications where backside finish is not critical
Edge Features	Bevel profile; edge rounding; edge exclusion (typically 2-3mm)	Edge rounding prevents chipping during handling; edge exclusion defines the non-process ring where lithography and deposition do not meet spec; exclusion width affects total die area per wafer
Orientation Mark	Notch (300mm standard); Primary + secondary flats (≤200mm)	Orientation marks provide crystal axis reference for automated handling and define wafer rotation in tools; laser-marked IDs provide lot/wafer traceability for MES integration
Cleanliness Grade	Prime (FEOL); Test/Monitor; Reclaim	Prime grade meets incoming QC for FEOL: low metals (<10¹⁰ atoms/cm²), low particles (<20 LPDs at 65nm threshold), low COP density; test/monitor grade used for equipment calibration and process monitoring; reclaim wafers are polished used wafers returned by the fab

Specialty Silicon Substrate Options

Type	Structure	Use Cases	Key Spec
SOI (Silicon-on-Insulator)	Thin Si device layer / buried SiO2 (BOX) / Si handle wafer	FD-SOI logic, RF front-end switches, silicon photonics, MEMS, power SOI	BOX thickness 10-200nm; device layer 5-200nm; device layer thickness uniformity ±0.5nm (FD-SOI)
High-Resistivity Silicon (HR-Si)	Standard CZ or FZ silicon at >1,000 Ω·cm	RF front-end modules (antenna switches, LNAs); low-crosstalk analog; CMOS image sensors	Resistivity uniformity across wafer; FZ required above ~5,000 Ω·cm; minority carrier lifetime spec for image sensor applications
Float Zone (FZ) Silicon	CZ-free growth; oxygen <10¹⁵ atoms/cm³; resistivity up to >30,000 Ω·cm	High-voltage IGBTs (>3.3kV), radiation detectors (CERN/HEP), ultra-high-resistivity RF	Oxygen content; minority carrier lifetime (ms range); max diameter 200mm (physics limit)
Epi-Ready Prime	Polished prime wafer with optimized surface chemistry for in-fab homoepitaxy	Fabs that grow their own epi layer in-house before FEOL processing begins	Low metallic contamination (<10¹⁰ atoms/cm²); surface roughness Ra <0.1nm; COP density spec

Compound & Specialty Wafer Orientations

Material	Common Diameters	Typical Orientation	Primary Applications
SiC (4H)	150mm (dominant); 200mm (ramping)	(0001) 4° off-axis toward [11-20]	Power MOSFETs, Schottky diodes, EV inverters; semi-insulating for GaN RF epi
GaN-on-Si	150mm; 200mm	GaN c-plane (0001) on Si (111)	Power HEMTs (EV chargers, data center PSUs), RF sub-6GHz
GaN-on-SiC	100mm; 150mm	GaN c-plane on SiC (0001)	RF power amplifiers (defense radar, 5G base stations, satellite)
GaAs	100mm; 150mm	(100) 2° off-axis	RF power amplifiers, VCSELs, 3D sensing, optoelectronics
InP	75mm; 100mm; 150mm (emerging)	(100) -- semi-insulating (Fe-doped) or conductive (S/Sn-doped)	Photonic integrated circuits, coherent optical transceivers, InP HEMTs (>100 GHz)
Sapphire (Al2O3)	100mm; 150mm; 200mm	a-plane, c-plane, or r-plane depending on application	GaN-on-sapphire LED templates; optical windows; RF isolation
Fused Silica / Borosilicate Glass	200mm; 300mm	N/A (amorphous)	MEMS, RF MEMS, interposers for heterogeneous integration, display backplanes

Epitaxy Configurations as Delivered

Epi Type	Substrate	Typical Thickness	Purpose
Silicon homoepitaxy	Polished Si	50nm-10µm	Latch-up suppression, gettering, low-defect device layer for CMOS; power epi drift layer
SiC epiwafer	4H-SiC substrate	2-20µm (drift layer)	Drift layer for SiC power MOSFETs and Schottky diodes; doping and thickness define blocking voltage
GaN HEMT epiwafer	Si, SiC, or sapphire	Buffer + GaN ~1-5µm + AlGaN barrier ~20-30nm	2DEG channel formation for RF and power GaN HEMTs
III-V photonics epiwafer	InP or GaAs	Multi-quantum-well stacks; total 1-5µm	Laser diodes, optical modulators, photodetectors; each layer engineered for bandgap and strain
SOI device film	SOI (Si/BOX/Si handle)	5-200nm device layer	FD-SOI planar transistors, RF switching, silicon photonics waveguides

Mechanical & Geometry Quick Reference

Orientation marks: 300mm wafers use a single orientation notch; wafers at 200mm and below use primary and secondary flats (primary flat indicates crystal orientation; secondary flat indicates conductivity type per SEMI standard). Bow and warp limits are specified per diameter and material -- incoming QC measures TTV and warp before stock-in. Edge exclusion is defined in the purchase order (typically 2-3mm) and directly affects usable die area per wafer. For compound wafers, bow at process temperature (not just ambient) is a critical additional specification -- SiC and GaN-on-Si epiwafers with post-epi bow must meet tool-specific chuck clamping tolerances.

Incoming QC: Dock to Stock

QC Step	What Is Checked	Method	Disposition if Fail
Visual inspection	Scratches, chips, contamination, packaging damage	Operator inspection under controlled lighting; 100% inspection	Reject to supplier; hold pending investigation
ID and orientation verification	Laser-marked wafer IDs match PO; notch/flat orientation correct	Automated barcode/OCR reader; notch sensor	Quarantine lot; supplier notification
Dimensional metrology	Thickness, TTV, bow, warp -- sampled from each lot	Capacitance gauge, interferometry, or optical profiler; typically 5 wafers per cassette sampled	Expanded sampling; 100% inspection; reject if systematic
Surface particle count	Light point defects (LPD) at specified detection threshold	Laser surface scanner (KLA SP-series, Hitachi IS-series); sampled	Reject wafer; incoming clean if contractually permitted
Metallic contamination audit	Surface metal ions (Fe, Cu, Ni, Na) at ppb or ppt level	VPD-ICP-MS (vapor phase decomposition + mass spectrometry); periodic audit, not 100%	Quarantine lot; root cause investigation with supplier
Epi characterization (if applicable)	Epi layer thickness and uniformity; resistivity/doping profile; surface roughness	Ellipsometry, reflectometry (thickness); four-point probe (resistivity); AFM (roughness); sampled	Reject epiwafer lot; supplier rework or replacement

Procurement Specification Requirements

A complete wafer purchase order must specify every attribute that affects process compatibility. Missing or ambiguous specifications result in disputes, incoming rejects, or worse -- wafers that pass incoming QC but cause yield issues later. For silicon wafers, the PO must define: diameter, crystal orientation (and off-axis angle if applicable), conductivity type, dopant species, resistivity range, thickness and TTV, surface finish (SSP or DSP), edge exclusion, notch or flat specification, laser-marked ID format, cleanliness grade, container type and capacity, and any epi layer structure. For compound wafers, add: substrate dislocation density (EPD for GaAs/InP, micropipe density for SiC), epi layer structure (each layer thickness, composition, doping), bow and warp limits at process temperature, and mechanical fragility handling requirements. For power device substrates (SiC, GaN), additionally define: micropipe specification, basal plane dislocation density limit, epi drift layer doping uniformity (±% across wafer), and breakdown voltage target for acceptance testing.

Incoming Containers

Container	Wafer Size	Capacity	Where Used	Notes
Shipping cassette / sealed box	All sizes	13-25 wafers	Vendor to fab receiving dock	Cleanroom-packaged at supplier; shock-protected; nitrogen-purged or vacuum-sealed options; opened in fab cleanroom only
SMIF Pod	150mm; 200mm	13-25 wafers	Stockroom to process tools in 200mm fabs	Standard Mechanical Interface pod; sealed mini-environment; mechanically interfaces with tool load ports; still the norm at 200mm facilities
FOUP	300mm	25 wafers	AMHS overhead transport to process tools in 300mm fabs	Front Opening Unified Pod; industry automation standard; nitrogen-purged; opens only at tool load port in cleanroom; integrates with fab MES for real-time tracking
Panel carrier / JLP	Panel format (various)	Panel dependent	Advanced fan-out packaging lines (panel-level packaging)	Used for panel-level packaging (PLP) -- not a front-end wafer format; included for completeness at the fab input boundary

Related Coverage