Semiconductor Photomasks & Reticles

A photomask -- also called a reticle -- is the precision template used in lithography to project a circuit layer pattern onto a wafer. Each mask corresponds to one patterning step in the process flow: transistor gate, contact, metal layer, via, and so on. Advanced SoCs require 70-100+ individual masks per design, with each mask layer requiring its own writing, inspection, repair, and qualification cycle before entering production. Photomasks are produced externally in specialized mask shops and delivered to fabs as finished deliverables, never fabricated in-line during wafer processing.

Mask Types

Mask Type	Wavelength	Structure	Node Range	Notes
Binary (Chrome-on-Quartz)	365nm i-line, 248nm KrF, 193nm ArF	Opaque chromium on quartz substrate; transmissive where chrome is absent	≥65nm; mature nodes, legacy ICs, packaging	Simplest mask type; lowest cost; persistent demand in automotive, IoT, analog, MEMS, and advanced packaging RDL layers
Phase-Shift Mask (PSM)	193nm ArF immersion	Semi-transparent phase-shifting regions create destructive interference at feature edges, sharpening image contrast	65nm-14nm; resolution enhancement beyond binary limits	Attenuated PSM most common; alternating PSM used for critical gate layers; increases write and inspection complexity and cost
EUV Mask (Reflective)	13.5nm EUV	Mo/Si multilayer reflector on ULE glass substrate; tantalum-based absorber patterned on top; reflective not transmissive	7nm and below; dominant at 5nm, 3nm, 2nm, and angstrom nodes	Requires defect-free blank from AGC or Hoya; pellicle required for production use; actinic inspection at 13.5nm for defect detection; most complex and expensive mask type
High-NA EUV Mask	13.5nm EUV (High-NA scanner, 0.55 NA)	Similar to standard EUV mask but different aspect ratio -- ASML High-NA tools use a half-field exposure, requiring masks that cover a smaller area per exposure; mask area per die effectively increases 40-60%	2nm and below; angstrom era (1.8nm, 1.4nm)	DNP began supplying evaluation masks for beyond-2nm nodes; new blank specifications required; pellicle design change needed for High-NA geometry; Intel EXE:5000 and EXE:5200B in use; TSMC received High-NA tools for 2nm ramp
Multi-Patterning Mask Sets	193nm ArF immersion	Multiple masks per layer, exposed sequentially (LELE, SADP, SAQP) to achieve feature pitches below single-exposure limits	14nm-7nm (pre-EUV critical layers)	2x to 4x more masks per layer than single-exposure; each mask in a multi-patterning set must be overlay-registered to the others; EUV reduces but has not eliminated multi-patterning for some layers at advanced nodes

Mask Set Complexity & Cost by Node

Node	Approx. Mask Count	Typical Mask Set Cost	Patterning Approach	Notes
65nm	~20-25	$0.2M-$0.5M	Single exposure, binary/PSM mix	Legacy automotive, IoT, analog; still in production volume
28nm	~30-35	$0.8M-$1.5M	Double patterning (193i) begins	Cost-sensitive SoC workhorse; highest volume mature node
16/14nm	~40-50	$1.5M-$3M	Quadruple patterning (193i); complex OPC	High mask count from multi-patterning; cost-driving transition node
7nm	~60-70	$3M-$6M (up to $15M per IBS data)	First EUV layers + residual multi-patterning	EUV adoption begins; first widespread use of EUV masks
5nm	~70-80	$6M-$12M	Heavy EUV usage; advanced pellicles	Apple A-series, flagship TSMC/Samsung designs; EUV dominant for critical layers
3nm	~85-100	$10M-$20M+	Mostly EUV; some double patterning at tightest pitches	Highest current production mask set complexity; actinic inspection required
2nm / 1.8nm (A14)	~100+	$15M-$30M+ (est.)	Low-NA EUV + early High-NA EUV for select critical layers	TSMC N2 in ramp; Intel 18A / 14A using High-NA EUV (EXE:5000 / EXE:5200B); High-NA masks in evaluation at DNP; mask set NRE costs approach or exceed design NRE at some geometries

Mask Manufacturing Process

Mask production flows through five sequential steps, each requiring specialized equipment and inspection. The cycle from design data to qualified mask delivered to a fab takes weeks to months depending on node complexity and defect repair requirements.

Step	Process	Key Equipment / Suppliers	Notes
1. Mask Writing	Electron-beam writer exposes resist on blank; creates the absorber pattern	NuFlare (JP) -- single-beam Gaussian; IMS Nanofabrication (AT) -- multi-beam mask writer (MBMW); JEOL (JP)	Multi-beam writers (IMS) dominate advanced node production; write times for complex EUV masks run 10-20+ hours per mask; write time is a throughput bottleneck
2. Development & Etch	Resist development; plasma or wet etch removes absorber in exposed regions	Standard semiconductor etch tools adapted for mask scale	EUV masks use tantalum nitride absorber etch chemistry rather than chrome; critical dimension uniformity across the mask area is the primary control metric
3. Inspection	Defect detection at die-to-database and die-to-die comparison; EUV masks require actinic inspection	KLA (US) -- optical and e-beam inspection; Lasertec (JP) -- actinic inspection (APMI, the only commercial EUV-wavelength inspector)	Lasertec's actinic tools are scarce with multi-year lead times; only actinic inspection detects phase defects in the Mo/Si multilayer invisible to optical tools; Lasertec is a secondary single-supplier chokepoint
4. Repair	Focused ion beam (FIB) or e-beam repair of detected defects; adds or removes absorber material locally	Zeiss (DE), NuFlare (JP)	Not all defects are repairable; defects in the Mo/Si multilayer below the absorber cannot be repaired -- the blank is scrapped; repairability window is narrowing at advanced nodes
5. Pellicle Mounting & Qualification	Pellicle frame attached; final inspection; mask loaded into reticle storage pod (RSP) for cleanroom delivery	Mitsui Chemicals (JP), S&S Tech (KR) for EUV pellicles; see EUV Mask Blanks & Pellicles	Masks are shipped in sealed RSPs with anti-static and vibration protection; in fab, automated stockers deliver to scanners; masks never contact open air once inside the fab

Mask Shop Supplier Landscape

Supplier	HQ	Est. Market Share	Strength	Key Notes
Toppan / Tekscend Photomask	Japan (rebranded Tekscend Nov 2024)	~15%	Advanced EUV masks; global fab footprint; R&D partnership with IBM for 2nm EUV mask development	Formerly Toppan Photomasks; rebranded to Tekscend for global recognition; one of two leading Japanese merchant mask houses; EUV qualified at TSMC, Samsung
Dai Nippon Printing (DNP)	Japan	~15%	EUV mask production; first to supply evaluation masks for beyond-2nm/High-NA EUV; advanced PSM	Alongside Tekscend, one of the two leading Japanese merchant mask houses; began supplying High-NA evaluation masks for angstrom-era nodes
Photronics	US	~18%	Largest independent mask shop globally; sub-10nm advanced node capability; US, Korea, Taiwan fabs	Only large-scale US-headquartered independent mask shop; serves logic, memory, and display; expanding capacity at advanced nodes
SK-Electronics	Japan	~5-8%	Specialized in advanced photomasks; EUV capability; close relationship with Japanese fabs	Focused niche supplier; not a broad-portfolio merchant house
TSMC / Samsung / Intel (Captive)	TW / KR / US	~30-35% combined (captive)	Internal mask capability for most critical layers at leading nodes; supply security; process integration advantage	All three leading IDMs/foundries operate internal mask shops; TSMC and Samsung in particular produce a significant share of their own EUV masks; even captive fabs use merchant shops for some layers and overflow capacity

High-NA EUV & the Angstrom Era

ASML's High-NA EUV scanner (TWINSCAN EXE platform, 0.55 NA) introduces new mask requirements that differentiate it from current low-NA EUV (0.33 NA). The High-NA tool uses a half-field exposure geometry -- the scanner images only half the standard mask field per shot -- which means each High-NA mask covers a smaller die area per exposure. This increases the number of masks required per layer for large dies and drives up mask area per wafer by an estimated 40-60% per mask. High-NA masks require new blank specifications and new pellicle designs to accommodate the different angle of incidence. DNP began supplying evaluation masks for beyond-2nm production. Intel has EXE:5000 and EXE:5200B tools in its D1X fab for development of 18A and 14A nodes, with high-volume manufacturing targeted from 2027. TSMC received High-NA tools for 2nm node development.

The stochastic challenge intensifies at High-NA. Thinner resists (below 30nm) required to maintain depth-of-focus reduce photon absorption, increasing shot noise and defect probability. Electron blur -- estimated at ~2nm -- becomes a meaningful fraction of the feature being patterned. Mask 3D effects (the finite thickness of absorber features at EUV wavelengths causes shadowing that distorts the printed pattern) worsen at High-NA angles. These are active engineering challenges at the frontier of what physics permits.

Photomask Deliverables - Usage in Fabs

Once delivered to a fab, a photomask is loaded into lithography scanners via automated reticle handling systems. A single mask may be used for thousands to hundreds of thousands of exposures before retirement -- mask lifetime varies with node, layer criticality, and pellicle usage. Mask defectivity is the most consequential quality variable: a defect that prints on every wafer exposed to that mask propagates yield loss across entire wafer lots before detection. EUV masks are particularly sensitive because phase defects in the Mo/Si multilayer can be invisible to optical inspection yet print at the wafer plane. At advanced nodes, mask qualification before production release involves extensive aerial image simulation, wafer print testing, and yield correlation -- a process that can take weeks per mask layer.

Supply Chain Outlook

The photomask supply chain is tightly coupled to EUV scanner deployment and node transitions. Each new node adds masks per design, each new EUV layer adds mask cost, and each High-NA tool deployment adds mask area requirements. The merchant mask shop landscape is concentrated -- Tekscend, DNP, Photronics, and SK-Electronics collectively serve the fabless and IDM customer base that cannot or does not self-supply -- with Japan home to the two leading advanced-node shops. The transition to High-NA EUV is opening a new qualification cycle for both mask shops and blank suppliers, with DNP positioned as the early mover for beyond-2nm evaluation masks. Mask set NRE costs at leading nodes are now large enough that they influence tape-out decisions and consolidate design activity toward high-volume applications that can amortize the investment.

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