Silicon Wafer Deliverables

A silicon wafer deliverable is a fab-ready substrate shipped from the wafer supplier to the semiconductor fab in a sealed, automated container. The wafer's diameter, substrate type, surface preparation, and doping specification are defined by the fab's process requirements and agreed upon through a wafer supply agreement. Wafer quality at delivery -- surface flatness, particle count, defect density, and contamination level -- directly sets the ceiling for lithography alignment accuracy, device yield, and reliability. A wafer that does not meet specification cannot be used without rework or scrap.

Wafer Diameter & Format

Diameter	Typical Use	Market Status	Notes
100mm (4-inch)	Legacy R&D, MEMS, compound semiconductor fabs	Declining; still used in specialty and research fabs	Some compound semiconductor and MEMS production remains on 100mm; most new capacity has migrated to 150mm or above
150mm (6-inch)	Analog, power devices, MEMS, SiC and GaN compound wafers	Widely used; critical for SiC power device production	SiC substrates are currently predominantly 150mm; silicon 150mm fabs serve analog and power markets with no near-term capacity addition pressure
200mm (8-inch)	Mixed-signal, analog, power, MEMS, IoT, automotive	Mainstream; strong and persistent demand; constrained capacity	200mm fab capacity is fully utilized for mature node products; new 200mm silicon wafer equipment is scarce; the Mature Node / $2 Chip Paradox is partly a 200mm capacity story -- see Mature Node MCU page
300mm (12-inch)	Leading-edge logic, DRAM, NAND flash, advanced foundry	Industry standard for advanced nodes; ~75% of silicon wafer market value	All Tier-1 logic and memory fabs; 30-40% cost-per-chip advantage over 200mm; Shin-Etsu Texas expansion, GlobalWafers capacity growth adding supply for CHIPS Act fabs
450mm (18-inch)	Proposed for cost scaling at future advanced nodes	R&D only; no commercial production; no firm industry timeline	Requires simultaneous commitment from TSMC, Samsung, Intel, and all tool suppliers; economics require near-perfect coordination; deferred indefinitely from original 2018 target

Wafer Types

Wafer Type	Structure	Primary Application	Key Suppliers	Notes
Polished (Prime) Silicon	CZ or FZ single-crystal silicon; mirror polished surface; p-type or n-type doped	Universal starting substrate for CMOS logic, memory, analog, and power devices	Shin-Etsu Chemical (JP), Sumco (JP), GlobalWafers (TW), Siltronic (DE), SK Siltron (KR)	Standard deliverable; sub-angstrom surface roughness; tight flatness (GBIR/SFQR) spec for advanced lithography
Epitaxial (Epi) Silicon	Thin single-crystal silicon layer grown by CVD on a polished substrate; independent doping from substrate	CMOS logic (reduces latch-up), power devices (higher purity active layer), advanced foundry where fab does not grow its own epi	Shin-Etsu Chemical (JP), Sumco (JP), Siltronic (DE), GlobalWafers (TW)	Epi wafers skip in-fab epitaxy step; epi layer thickness typically 1-10µm; price premium over polished wafer; heavy-p substrate with lightly-doped p-epi is standard for bulk CMOS
SOI (Silicon-on-Insulator)	Thin silicon device layer over a buried oxide (BOX) layer on a silicon handle wafer; typically 5-100nm Si over 25-200nm BOX	FD-SOI for low-power and RF (28nm FD-SOI, 22FDX); RF-SOI for smartphone front-end switches; FinFET and FDSOI logic; radiation-hardened defense ICs	Soitec (FR) -- near-monopoly on FD-SOI and RF-SOI; also GlobalWafers and Shin-Etsu for some SOI variants	Soitec's Smart Cut technology bonds a thin silicon layer to an oxidized handle wafer; BOX provides device isolation and eliminates substrate leakage; critical for FD-SOI foundry nodes (STMicroelectronics, GlobalFoundries 22FDX)
Strained Silicon / Ge-on-Si	Silicon under biaxial tensile strain (from SiGe virtual substrate) or germanium layer on silicon; bandgap and mobility engineered	Advanced CMOS mobility enhancement; SiGe channels in FinFET and gate-all-around transistors; Ge photodetectors integrated on silicon	Soitec (engineered substrates); also grown in-fab by leading logic foundries (TSMC, Samsung, Intel) as part of process integration rather than purchased as a deliverable	More commonly an in-fab process step (SiGe epitaxy) than a delivered wafer; engineered substrate variants from Soitec serve specific applications
Test / Monitor Wafers	Lower-specification polished silicon; may be recycled prime wafers or purpose-made monitor grade	Equipment calibration, process tuning, particle monitoring, endpoint detection qualification -- used before running prime product wafers	Same silicon wafer suppliers; also recycled wafer specialists (Entegris RegenSi program)	Fabs consume large quantities of test wafers -- a significant cost center; wafer reclaim programs recover and re-polish used test wafers for repeated use

Surface Preparation & Specification

A prime polished wafer delivered to a fab must meet exacting surface specifications across several dimensions. Global flatness (GBIR -- Global Back-side Ideal Range) measures the maximum deviation of the front surface from a reference plane across the full wafer; typical GBIR for 300mm prime wafers is below 2µm. Site flatness (SFQR -- Site Front-side least sQuares Range) measures flatness within each exposure site (typically 26mm × 33mm) and must be below 130nm for advanced ArF immersion lithography. Surface roughness (Ra) for polished prime wafers is below 0.1nm RMS. Particle counts (LPD -- Light Point Defects) are specified at sub-50nm detection threshold. Crystal-originated pits (COPs) from CZ oxygen precipitation are specified by density and maximum size. Orientation marks -- a notch at 300mm, a flat at smaller diameters -- provide crystal axis reference for automated handling.

Shipping & Handling

Container	Wafer Size	Capacity	Notes
FOUP (Front Opening Unified Pod)	300mm	25 wafers	Industry-standard sealed carrier; integrates with fab AMHS (automated material handling system) overhead transport; opened only at tool load port in cleanroom; nitrogen-purged to prevent oxidation
SMIF Pod (Standard Mechanical Interface)	200mm and smaller	25 wafers	Mini-environment carrier for 200mm fabs; mechanically interfaces with tool load ports; older standard than FOUP but still the norm at 200mm fabs
Open Cassette (shipping)	All sizes (in sealed outer packaging)	25 wafers	Wafer cassettes sealed in nitrogen-purged bags inside rigid shipping boxes with vibration-damped cushioning; opened only in cleanroom; humidity and ESD controlled

Once inside the fab, wafers are transferred into FOUPs or cassettes and routed by the automated material handling system (AMHS) via overhead conveyor to process tools. Wafers never contact open cleanroom air -- all transfers occur at load ports with controlled micro-environments. Compound wafers (GaAs, InP, SiC, GaN epiwafers) use the same carrier formats but may require additional handling precautions for fragility (InP, GaAs) or toxicity (arsenic, phosphorus compound waste streams).

Representative Silicon Wafer Suppliers

Supplier	HQ	300mm Share	Key Deliverable Types
Shin-Etsu Chemical (SEH)	Japan	~27%	Polished prime, epi, SOI; 300mm and 200mm; Texas expansion for CHIPS Act fabs
Sumco	Japan	~24%	Polished prime, epi; 300mm and 200mm; advanced DRAM and GPU-optimized wafers
GlobalWafers	Taiwan	~17%	Polished prime, epi, SOI, specialty epi with RF and power structures; 300mm and 200mm
Siltronic	Germany	~12%	Polished prime, epi, SOI; 300mm and 200mm; European supply anchor
SK Siltron	South Korea	~9%	Polished prime, epi; 300mm and 200mm; primary supplier into Samsung memory and foundry; also SiC epiwafers
Soitec	France	Specialty (SOI focus)	FD-SOI, RF-SOI, engineered substrates; near-monopoly on FD-SOI for STMicro and GlobalFoundries 22FDX; Smart Cut technology

Supply Chain Outlook

300mm silicon wafer supply is structurally tight for advanced node demand, with Shin-Etsu and Sumco holding approximately 50% of global capacity and qualification cycles of 2-4 years preventing rapid diversification. The 200mm market faces a different constraint: established fabs are fully utilized, new 200mm equipment is scarce since the industry stopped building new 200mm infrastructure when 300mm became the leading-edge standard, and the automotive and IoT demand surge has not been met with proportional new supply. SOI wafers remain effectively a Soitec near-monopoly for FD-SOI and RF-SOI, which is a quiet but significant concentration risk for the specific foundry nodes that depend on it.

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