Back-End Assembly & Packaging

Back-end assembly is the third segment of the four-segment manufacturing flow. The tested, sorted wafer arrives from wafer sort; the packaged, system-ready chip exits to module integration or directly to board-level assembly. Between those two points, the wafer is diced into individual dies, the dies are bonded to substrates, electrical connections are formed (by wire bond, flip-chip, or hybrid bonding), the package is encapsulated, and each packaged part is tested.

The concentration story in this segment lives at two levels. At the traditional packaging level, the outsourced assembly and test (OSAT) market is a five-company oligopoly led by ASE, Amkor, and JCET — who together hold more than 60% of the OSAT market. At the advanced packaging level, TSMC's CoWoS capacity is the single binding supply constraint on the global AI accelerator market: every NVIDIA H200, B-series, and Rubin GPU, every AMD MI300 and MI400 series accelerator, depends on TSMC CoWoS capacity. Ajinomoto Build-up Film (ABF) is near-sole-sourced for advanced substrate laminate. Hybrid bonding equipment is concentrated at BESI and Applied Materials. Back-end is no longer the commodity step it was a decade ago — it is now one of the hardest chokepoints in semiconductor manufacturing.

The Assembly Sequence

Back-end assembly runs as a sequential flow, not a loop. Each step happens once per die or once per package. The canonical sequence applies across both traditional packaging and most advanced packaging architectures, with advanced packaging adding interposer construction, multi-die bonding, and through-silicon-via (TSV) steps between die attach and encapsulation.

Traditional Assembly & Packaging Steps

Traditional packaging — wire-bonded QFN, BGA, LQFP, DIP parts — remains the dominant packaging format by unit volume. Every $2 MCU, every analog amplifier, every power management IC, every automotive MCU ships in a traditional package. The equipment supply for these steps is less concentrated than advanced packaging because multiple vendors compete at each tool category, but die bonders and wire bonders still concentrate at three global suppliers: ASMPT, Kulicke & Soffa, and BESI.

Advanced Packaging

Advanced packaging is the second track inside back-end, differentiated from traditional packaging by multi-die integration, interposer use, and in many cases wafer-level rather than die-level processing. The architectural landscape splits across fan-out wafer-level packaging (FOWLP), 2.5D (dies side-by-side on an interposer or bridge), and 3D (stacked dies with through-silicon vias). Each foundry has its own branded implementations: TSMC leads in CoWoS and InFO, Intel in EMIB and Foveros, Samsung in I-Cube and SAINT, SK hynix in HBM stacking. The full sub-architecture catalog lives at Advanced Packaging Overview; the table below maps the primary architectures by concentration.

Package Types Spectrum

The package type spectrum runs from a sub-dollar wire-bonded QFN to a $30,000+ CoWoS multi-die AI accelerator package. Cost, complexity, and interconnect density grow together along this spectrum. Different chip categories sit at different points — a mature-node MCU ships in QFN or BGA; a mobile SoC ships in FO-WLP; an AI accelerator ships in CoWoS or Foveros; an HBM stack ships as a 3D-bonded DRAM tower.

OSAT Concentration

The outsourced assembly and test industry is a five-company oligopoly that handles the packaging and test for most fabless semiconductor companies and for the mature-node portion of IDM production. OSATs are concentrated in Taiwan, China, and Southeast Asia. The top three — ASE, Amkor, and JCET — together hold more than 60% of global OSAT revenue. OSAT landscape covers the full operator catalog.

Advanced Packaging Material Bottlenecks

Advanced packaging depends on a small number of input materials and tools, each of which has become a structural supply constraint as the AI accelerator and HBM buildout has accelerated. The Bottleneck Atlas covers the full cross-pillar view; the table below lists the back-end-specific bottlenecks.

In-House vs. Outsourced Packaging

A decade ago, packaging was almost universally outsourced to OSATs. The rise of advanced packaging has changed this. TSMC built CoWoS and InFO as in-house capabilities because the process integration requirements with front-end fabrication are too tight to hand off. Intel runs EMIB and Foveros in-house for the same reason. Samsung runs I-Cube and SAINT in-house. SK hynix packages its own HBM stacks. The result is a bifurcated back-end: traditional packaging remains OSAT-dominated, advanced packaging concentrates at foundry and IDM captive lines.

This is the industry dynamic behind the Terafab vertical integration thesis: for strategic programs where packaging, front-end, and design must co-optimize, in-house packaging is the only viable answer. For commodity parts where cost amortization dominates, OSAT remains the right model.

Where Back-End Assembly Happens

Back-end assembly is geographically more diversified than leading-edge front-end fabrication, but still concentrated in East Asia. Taiwan and China together account for over 60% of global packaging capacity. Southeast Asia (Malaysia, Philippines, Vietnam, Thailand) hosts significant OSAT capacity for the cost-sensitive tier. The United States is ramping advanced packaging capacity under CHIPS Act incentives (Amkor Arizona, TSMC Arizona captive advanced packaging). Europe hosts limited packaging capacity; Japan retains specialty and memory packaging.

Related Coverage

Parent: Manufacturing Flow Hub

Peers in flow: Front-End Fabrication · Wafer Test (Sort) · Module Integration

Sub-hubs: Back-End Assembly · Advanced Packaging

Back-end assembly children: Dicing · Die Attach · Bonding Overview (Wire · Flip-Chip) · BEOL Materials · Encapsulation · Final Test

Advanced packaging children: CoWoS · InFO · Foveros · EMIB · 3D IC · Advanced Interconnects · Substrates & Interposers · Advanced Packaging Test

Operator landscape: OSAT Landscape (serves both traditional assembly and advanced packaging)

Cross-pillar dependencies: HBM · AI Accelerators (CoWoS consumers) · Bottleneck Atlas · Tesla Terafab (vertical integration thesis)